UltraScale architecture-based devices provide various I/O offerings: High-performance (HP), high-density (HD), and high-range (HR) I/O banks.
• The HP I/O banks are designed to meet the performance requirements of high-speed memory and other chip-to-chip interfaces with voltages up to 1.8V.
• The HR I/O banks are designed to support a wider range of I/O standards with voltages up to 3.3V.
• The HD I/O banks are designed to support low-speed interfaces.
UltraScale devices contain different combinations of HP, HD, and HR I/O banks, and not all types of banks are supported in all devices. The UltraScale Architecture and Product Overview (DS890) [Ref 3] documents the available number of each type of bank for all devices.
• Kintex UltraScale and Virtex UltraScale families have high-performance I/O banks (HP I/Os) and high-range I/O banks (HR I/Os) with corresponding logic resources.
° SelectIO Interface Resources describes the electrical behavior of the output drivers and input receivers, and gives detailed examples of many standard interfaces available in these devices.
° SelectIO Interface Logic Resources describes the I/O logic resources available in these devices.
° Any references to Mobile Industry Processor Interface (MIPI) D-PHY or HD I/O in these chapters do not apply to these devices.
• The Zynq UltraScale+, Artix UltraScale+, Kintex UltraScale+, and Virtex UltraScale+ families have high-performance I/O banks (HP I/Os) with enhanced MIPI D-PHY abilities and the corresponding logic resources. They also have high-density I/Os (HD I/Os) with corresponding logic resources.
° SelectIO Interface Resources describes the electrical behavior of the output drivers and input receivers, and gives detailed examples of many standard interfaces available in these devices for HP I/Os.
° SelectIO Interface Logic Resources describes the I/O logic resources available in these devices for HP I/Os.
° High Density I/O Resources describes the electrical and logical features of HD I/Os that are available in Zynq UltraScale+ devices, Artix UltraScale+ FPGAs, Kintex UltraScale+ FPGAs, and some Virtex UltraScale+ FPGAs.
° Any references to HR I/Os in the aforementioned chapters do not apply to these devices.
Outside the aforementioned information, the content in the rest of this chapter does not pertain to HD I/Os. HD I/O information is only described in High Density I/O Resources .
Table: Supported Features in the HR and HP I/O Banks highlights the features supported in the HP and HR I/O banks. See the specific UltraScale device data sheets [Ref 2] for details on the performance and other electrical requirements of the HP and HR I/O banks.
Feature |
HP I/O Banks |
HR I/O Banks |
---|---|---|
3.3V I/O standards (1) |
N/A |
Supported |
2.5V I/O standards (1) |
N/A |
Supported |
1.8V I/O standards (1) |
Supported |
Supported |
1.5V I/O standards (1) |
Supported |
Supported |
1.35V I/O standards (1) |
Supported |
Supported |
1.2V I/O standards (1) |
Supported |
Supported |
1.0V POD I/O standard |
Supported |
N/A |
LVDS signaling |
Supported (2) |
Supported |
Digitally-controlled impedance (DCI) and DCI cascading |
Supported |
N/A |
Internal V REF |
Supported |
Supported |
Internal differential termination (DIFF_TERM) |
Supported |
Supported |
IDELAY |
Supported |
Supported |
ODELAY |
Supported |
Supported |
IDELAYCTRL |
Supported |
Supported |
ISERDES |
Supported |
Supported |
OSERDES |
Supported |
Supported |
Transmitter pre-emphasis |
Supported |
Supported (3) |
Receiver equalization |
Supported |
Supported |
Receiver offset control |
Supported |
Not supported |
Receiver V REF scan |
Supported |
Not supported |
MIPI D-PHY |
Supported in Virtex UltraScale+, Kintex UltraScale+, Artix UltraScale+, and Zynq UltraScale+ devices |
Not supported |
Notes: 1. The I/O Bank Type column in Table: Attribute Options, Bidirectional Buffer Availability, and DCI Termination Type shows the specific I/O standards that are available in the HP and HR I/O banks. 2. Although LVDS is generally considered a 2.5V I/O standard, it is supported in both the HR and HP I/O banks. |