Previous AMD Adaptive Computing FPGA families featuring DCI used a slightly different circuit for calibrating the controlled impedance driver and split-termination impedance from the external reference resistors placed on the VRN and VRP pins. In AMD 7 series FPGAs, DCI calibrated each leg of the split-termination circuit to be directly equal to the external resistor values. For example, a 7 series device with a target parallel termination of 50 Ω to V CCO /2 requires 100 Ω external resistors on the VRN and VRP pins.
In UltraScale devices, irrespective of the DCI termination value requirement, the external resistor on the VRP pin is required to be 240 Ω . Instead of two resistors, only one resistor is required at an UltraScale device VRP pin. The exact value of the split-termination or single-termination resistors are determined by the user-controllable ODT attribute.
Possible ODT values for split-termination DCI standards (HSTL and SSTL) are RTT_40, RTT_48, or RTT_60.
IMPORTANT: The ODT value represents the desired Thevenin resistance to V CCO /2 for split-termination DCI standards.
Possible ODT values for single-termination POD standards are RTT_40, RTT_48, or RTT_60. Possible ODT values for single-termination HSUL standards are RTT_120, RTT_240, or RTT_NONE.
IMPORTANT: The ODT value represents the desired resistance to V CCO for single-termination DCI standards.
The termination value for the controlled impedance driver is determined by the DCI state machine when a DCI standard with a controlled impedance driver is chosen, using OUTPUT_IMPEDANCE attribute values. Possible values for OUTPUT_IMPEDANCE attributes are RDRV_40_40, RDRV_48_48, RDRV_60_60, and RDRV_NONE_NONE.