1. UltraFast Design Methodology Guide for the Vivado Design Suite ( UG949 )
2. UltraScale Architecture Packaging and Pinout User Guide ( UG575 )
3. UltraScale Architecture SelectIO Resources User Guide ( UG571 )
4. Vivado Design Suite User Guide: Using Constraints ( UG903 )
5. UltraScale and UltraScale+ device data sheets :
° UltraScale Architecture and Products Overview ( DS890 )
° Zynq UltraScale+ MPSoC Overview ( DS891 )
° Kintex UltraScale Architecture Data Sheet: DC and AC Switching Characteristics ( DS892 )
° Virtex UltraScale Architecture Data Sheet: DC and AC Switching Characteristics ( DS893 )
° Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics ( DS922 )
° Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics ( DS925 )
° Virtex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics ( DS923 )
° Artix UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics ( DS931 )
6. MMCM and PLL Dynamic Reconfiguration ( XAPP888 )
7. UltraScale Architecture Libraries Guide ( UG974 )
8. LogiCORE IP Clocking Wizard User Guide ( PG065 )
9. UltraFast Design Methodology Quick Reference Guide ( UG1231 )
10. UltraFast Design Methodology Checklist ( XTP301 )
11. Zynq UltraScale+ MPSoC Packaging and Pinout User Guide ( UG1075 )
12. Zynq UltraScale+ MPSoC Technical Reference Manual ( UG1085 )
13. Vivado Design Suite User Guide ( UG908 )
The following table shows the revision history for this document.
|
Date |
Version |
Revision |
|---|---|---|
|
02/01/2023 |
1.10.2 |
Editorial updates only. No technical content updates. |
|
08/25/2021 |
1.10.1 |
Editorial updates only. No technical content updates. |
|
08/28/2020 |
1.10 |
Chapter 3 : Updated This Figure . Updated the table for register 15 in MMCM Registers . |
|
10/31/2019 |
1.9 |
Chapter 3 : Updated Table: MMCM Attributes footnote. Updated Spread-Spectrum Clock Generation section with new content and equations. Updated Table: PLL Attributes . Updated UltraScale+ note on page 30 . |
|
12/19/2018 |
1.8 |
Chapter 3 : Updated the example in Determine the Input Frequency section. Added the new sections Dynamic Reconfiguration Port and Clocking Guidelines . |
|
04/09/2018 |
1.7 |
Chapter 2 : Updated the BUFG_GT and BUFG_GT_SYNC section. Chapter 3 : In Table: MMCM Attributes , updated note 3 . |
|
06/06/2017 |
1.6 |
Chapter 3 : In Table: MMCM Attributes , updated the description of BUF_IN for the COMPENSATION attribute on page 53 . |
|
03/15/2017 |
1.5 |
Chapter 2 : Updated the discussion on page 13 . Added clarification to the BUFG_GT and BUFG_GT_SYNC section. Chapter 3 : Updated the Dynamic Phase Shift Interface in the MMCM section. Added Table: Manual SS Timing Adjustment Using Input Frequency for UltraScale+ Devices and Table: Spread-Spectrum Generation Restrictions for UltraScale+ Devices . In Table: PLL Attributes , updated the descriptions for CLKOUT[0:1]_PHASE and CLKFBOUT_PHASE . |
|
12/12/2016 |
1.4 |
Chapter 1 : Updated the discussion on page 7 about the differences between clock capable and global clock pins. Chapter 2 : Added clarification to the Global Clock Inputs section. Added further information following This Figure . Updated the BUFGCE_DIV section. Revised the BUFG_GT_SYNC description on page 31 to include the UltraScale+ devices. Chapter 3 : Added the UltraScale+ device MMCME4 and PLLE4 primitives to the MMCM Primitives and PLL Primitives sections. Updated the description of PSCLK cycles in the Dynamic Phase Shift Interface in the MMCM section. Added a Recommended note on page page 49 . Updated the CLKINSTOPPED – Input Clock Status section. Added CLKFBOUT and CLKFBIN to Table: PLL Ports and their descriptions below the table. Updated the CLKOUTPHYEN – PHY Clock Enable description. Added This Figure and This Figure . In Table: PLL Attributes , updated the DIVCLK_DIVIDE allowed values and added PHY_ALIGN to the COMPENSATION attribute. Updated the Please Read: Important Legal Notices section. |
|
11/24/2015 |
1.3 |
Under Introduction to UltraScale Architecture , added new introductory text for UltraScale+ devices. Added ninth bullet under Key Differences from 7 Series FPGAs . Updated first paragraph under Global Clock Inputs to include information about HDGC pins. Updated first paragraph under Clock Structure . Added Important note under Clock Buffers . Added second paragraph under BUFCE_LEAF Clock Buffer . Added first two sentences under BUFG_GT and BUFG_GT_SYNC . Added BUFG_PS section. Updated Frequency Synthesis Using Fractional Divide in the MMCM , by changing 0.125 degrees to 0.125. Revised the heading Static Phase Shift Mode (MMCM and PLL) by adding (MMCM and PLL). Revised the heading MMCM Clock Divide Dynamic Change by adding MMCM. Added Important note under CLKFBIN – Feedback Clock Input . In Table: MMCM Attributes , added a row of UltraScale+ device MMCM attributes for CLKFBOUT_MULT_F(1) , changed default value for COMPENSATION from ZHOLD to AUTO, revised the COMPENSATION Description, added note 4 , and note 5 . In Table: PLL Attributes , added a row of UltraScale+ device PLL attributes for CLKFBOUT_MULT , revised the COMPENSATION Description, and added note 1 . Added Dynamic Reconfiguration Port section. Updated References . |
|
02/23/2015 |
1.2 |
In Table: MMCM Attributes , changed the Allowed Values attribute for CLKIN1_PERIOD and CLKIN2_PERIOD . In Table: PLL Attributes , changed the Allowed Values attribute for CLKIN_PERIOD . |
|
08/21/2014 |
1.1 |
Replaced clock-capable with global clock in Global Clock Inputs . Updated Byte Clock Inputs . Added BUFG_GT_SYNC to BUFG_GT and BUFG_GT_SYNC . Updated This Figure and added tip for Table: MMCM Ports(1) . Updated This Figure . |
|
12/10/2013 |
1.0 |
Initial Xilinx release. |