Upon configuring the device, if enabled, the PCI Express cores are visible in the Vivado Hardware Manager.
The PCI Express LTSSM debug content is shown in an LTSSM State Transition Diagram. This interface displays an ordered list of the LTSSM state transitions showing which states are visited and a diagram illustrating the visited states and currently occupied states in the LTSSM.
Figure 1. PCI Express Link Debug Interface
