JTAG Fallback Support - 2024.1 English

Vivado Design Suite User Guide: Programming and Debugging (UG908)

Document ID
UG908
Release Date
2024-05-30
Version
2024.1 English

The XVC based debug solution can be used with AXI masters such as the PCIe® XDMA IP. If the AXI master is in a hang situation or is otherwise not functioning properly, there are no methods to debug those scenarios. To provide a JTAG-based fall back debug pathway that is parallel to the XVC pathway, AMD recommends using the Debug Bridge in BSCAN Primitive mode. A Debug Bridge in BSCAN Primitive mode can be instantiated in static region and its BSCAN master interface can be connected to the BSCAN slave interface of a second Debug Bridge that is configured with the JTAG Fallback Support enabled. There are two JTAG Fallback Support types:

  1. If the Debug Bridge that you want to provide JTAG Fallback for resides in a RP region, you need to enable the External BSCAN Master JTAG Fallback Support.
  2. If the Debug Bridge that you want to provide JTAG Fallback for resides in the static region (or in a flat design), you should enable the Internal BSCAN Master JTAG Fallback Support.