PCI Express Link Debug - 2024.1 English

Vivado Design Suite User Guide: Programming and Debugging (UG908)

Document ID
UG908
Release Date
2024-05-30
Version
2024.1 English

The Versal PCI Express® Integrated Block in Vivado supports link debug. If enabled, the core stores the Link Training and Status State Machine (LTSSM) state transitions which is accessible in the Vivado Hardware Manager.