In-System Logic Design Debugging - 2024.1 English

Vivado Design Suite User Guide: Programming and Debugging (UG908)

Document ID
UG908
Release Date
2024-05-30
Version
2024.1 English

The Vivado Design Suite also includes a logic analysis feature that enables you to perform in-system debugging of the post-implemented design in an FPGA or adaptive SoC. The benefits of debugging your design in-system include debugging your timing-accurate, post-implemented design in the actual system environment at system speeds. The limitations of in-system debugging include somewhat lower visibility of debug signals compared to using simulation models and potentially longer design/implementation/debug iterations, depending on the size and complexity of the design.

In general, the Vivado tool provides several different ways to debug your design. You can use one or more of these methods to debug your design, depending on your needs. In-System Logic Design Debugging Flows focuses on the in-system logic debugging capabilities of the Vivado Design Suite.