Synplify mark_debug Syntax Examples - 2024.1 English

Vivado Design Suite User Guide: Programming and Debugging (UG908)

Document ID
UG908
Release Date
2024-05-30
Version
2024.1 English

The following are examples of Synplify syntax for VHDL, Verilog, and SDC.

  • VHDL Syntax Example
    attribute syn_keep : boolean;
    attribute mark_debug : string;
    attribute syn_keep of char_fifo_dout: signal is true;
    attribute mark_debug of char_fifo_dout: signal is "true";
  • Verilog Syntax Example
    (* syn_keep = "true", mark_debug = "true" *) wire [7:0] char_fifo_dout;
  • SDC Syntax Example
    define_attribute {n:char_fifo_din[*]} {mark_debug} {"true"}
    define_attribute {n:char_fifo_din[*]} {syn_keep} {"true"}
    Important: Net names in an SDC source must be prefixed with the "n:" qualifier.
    Note: Synopsys Design Constraints (SDC) is an accepted industry standard for communicating design intent to tools, particularly for timing analysis. A reference copy of the SDC specification is available from Synopsys by registering for the TAP-in program by clicking this link.