Vivado Synthesis mark_debug Syntax Examples - 2024.1 English

The following are examples of VHDL and Verilog syntax when using Vivado synthesis.

• VHDL Syntax Example

  attribute mark_debug : string;
  attribute mark_debug of char_fifo_dout: signal is "true";

• Verilog Syntax Example

  (* mark_debug = "true" *) wire [7:0] char_fifo_dout;