There are five modes in the Debug Bridge that are used in Xilinx Virtual Cable (XVC) implementations.
- From AXI to BSCAN
- In this mode, the Debug Bridge receives XVC Commands via AXI4-Lite slave interface.
- From JTAG to BSCAN
- In this mode, the Debug Bridge receives XVC Commands via JTAG slave interface driven by user logic.
- From PCIe to BSCAN
- In this mode, the Debug Bridge receives XVC Commands via PCIe Extended Configuration slave interface.
- From PCIe to JTAG
- In this mode, the Debug Bridge receives XVC Commands via PCIe Extended Configuration interface. This Debug Bridge brings out the JTAG pins out of the FPGA through I/O pins. This mode is mainly used to debug design on another board over XVC.
- From AXI to JTAG
- In this mode, the Debug Bridge receives XVC commands via AXI4-Lite interface to send over the JTAG pins to a target device.
In all of these modes the Debug Bridge can further communicate with other debug cores/ Debug Bridge instances in the design via the Soft-BSCAN (Boundary Scan) interface. The Soft BSCAN master interface enables extension of the JTAG interface to internal USER defined scan chains/Debug Bridge instances.