Connecting to the Hardware Target and Programming the Device - 2024.1 English

Vivado Design Suite User Guide: Programming and Debugging (UG908)

Document ID
UG908
Release Date
2024-05-30
Version
2024.1 English

Programming an FPGA or adaptive SoC prior to debugging involves exactly the same steps described in Programming the FPGA or adaptive SoC. After programming the device with the .pdi file that contains the IBERT core, the Hardware window now shows the components of the IBERT core with the RTL instance name shown in parenthesis, which were detected when scanning the device (see the following figure).

Important: In designs using the In-System IBERT IP for UltraScale and UltraScale+ designs, you see the In-System IBERT core being detected in the Hardware window.
Figure 1. Hardware Window Showing the IBERT Core