Disabling Control Registers Setup - 2024.1 English

To disable the Control Register programming, run the following Tcl command:

program_hw_devices -control_efuse {20} [lindex [get_hw_devices] $deviceIdx]

Where $deviceIdx is set to the index of the UltraScale or UltraScale+ device on which you are disabling the eFUSE Control Register bit programming.

This sets the W_DIS_CNTL bit, which in turn disables further eFUSE Control Register bit programming.

In the Security Register Setup wizard pane, specify the following settings:

Figure 1. eFUSE Security Register Setup

In the Security Register Setup wizard pane specify security control options over the type of bitstreams allowed to load on the FPGA. The FUSE_SEC settings are:

• CFG_AES_Only: When set, only accept encrypted bitstreams.
• EFUSE_KEY_Only: When set, only the eFUSE key can be used for decryption.
• RSA_AUTH: When set, forces RSA Authentication of bitstreams.
• SCAN_DISABLE: When set, disables AMD access to internal test registers.
• CRYPT_DISBALE: When set, permanently disables the decryptor.

For more details on the FUSE_SEC register, refer to the UltraScale Architecture Configuration User Guide (UG570).

Review the eFUSE settings in the Program eFUSE Registers Summary pane.

Figure 2. Program eFUSE Registers Summary

All bits set in the Program eFUSE Registers wizard panels are shown in this pane. In this pane you see individual bit settings to review the specific programming settings. Carefully review this summary page to ensure every bit that is intended to be programmed is set.

Click Finish to bring up the Program eFUSE confirmation dialog box:

Figure 3. Program eFUSE Confirmation Dialog

Click OK to program the specified fuse bits.