AXI4 Debug Hub - 2024.1 English

Vivado Design Suite User Guide: Programming and Debugging (UG908)

Document ID
UG908
Release Date
2024-05-30
Version
2024.1 English

Versal devices use the AXI4 Debug Hub, which is similar to the debug hub used in previous architectures and provides connectivity between the Versal Control, Interface, and Processing (CIPS) IP and the debug cores in the design. In previous architectures Vivado inserts this core automatically without user intervention. It is also possible to manually instantiate the AXI4 Debug Hub. Manual instantiation is only recommended if using DFX, or the design's addressing scheme that requires setting a manual address for the AXI4 Debug Hub.