Using the Netlist Insertion Debug Probing Flow - 2023.2 English

Vivado Design Suite User Guide: Programming and Debugging (UG908)

Document ID
UG908
Release Date
2023-10-19
Version
2023.2 English

Insertion of debug cores in the Vivado tool is presented in a layered approach to address different needs of the diverse group of Vivado users:

  • The highest level is a simple wizard that creates and configures Integrated Logic Analyzer (ILA) cores automatically based on the selected set of nets to debug.
  • The next level is the main Debug window allowing control over individual debug cores, ports, and their properties. The Debug window can be displayed when the Synthesized Design is open by selecting the Debug layout from the Layout Selector or the Layout menu or can be opened directly using Window > Debug.
  • The lowest level is the set of Tcl XDC debug commands that you can enter manually into an XDC constraints file or replay as a Tcl script.

You can also use a combination of modes to insert and customize debug cores.