Waveform and AXI Interfaces - 2024.1 English

Vivado Design Suite User Guide: Programming and Debugging (UG908)

Document ID
UG908
Release Date
2024-05-30
Version
2024.1 English

The System ILA debug core enables you to debug and monitor interfaces as slots. Each slot corresponds to an interface being debugged in IP integrator Block Design. In the following figure, there are two AXI Memory Map interfaces being probed by the System ILA IP in slot 0, slot 1.

Figure 1. Probing 2 AXI Memory Map Interfaces