Instantiating the Debug Cores - 2024.1 English

After generating the debug core, instantiate it in your HDL source code and connect it to the signals that you wish to probe for debugging purposes. Following is an example of the ILA instance in a Verilog HDL source file:

u_ila_0 
(
 .clk(clk),
 .probe0(counterA),
 .probe1(counterB),
 .probe2(counterC),
 .probe3(counterD),
 .probe4(A_or_B),
 .probe5(B_or_C),
 .probe6(C_or_D),
 .probe7(D_or_A)
);