System Generator is a DSP design tool from Xilinx® that enables the use of the MathWorks model-based Simulink® design environment for FPGA design. Previous experience with Xilinx FPGAs or RTL design methodologies are not required when using System Generator. Designs are captured in the DSP friendly Simulink modeling environment using a Xilinx specific blockset. The System Generator design can then be imported into a Vivado® IDE project using the IP catalog.
Refer to the Vivado Design Suite Tutorial: Model-Based DSP Design Using System Generator (UG948) for hands-on lab exercises and step-by-step instruction on how to create a System Generator for DSP model and then import that model into a Vivado IDE project.