SysgenPortDescriptor provides methods for configuring individual ports. For example, assume port dout is unsigned, 12 bits, with binary point at position 8. The code below shows one way in which this type can be defined.
dout = this_block.port('dout');
dout.setWidth(12);
dout.setBinPt(8);
dout.makeUnsigned();
The following also works:
dout = this_block.port('dout');
dout.setType('Ufix_12_8');
The first code segment sets the port attributes using individual method calls. The second code segment defines the signal type by specifying the signal type as a string. Both code segments are functionally equivalent.
The black box supports HDL modules with 1-bit ports that are declared using either single bit
port (e.g., std_logic) or vectors (e.g., std_logic_vector(0
downto 0)) notation. By default, System Generator assumes ports to be
declared as vectors. You may change the default behavior using
the useHDLVector method of the descriptor. Setting this method
to true tells System Generator to interpret the port as a vector. A false
value tells System Generator to interpret the
port as single bit.
dout.useHDLVector(true); % std_logic_vector
dout.useHDLVector(false); % std_logic