When translated into hardware, System Generator's Gateway In and Gateway Out blocks become input and output ports. The locations of these ports and the speeds at which they must operate can be entered in the Gateway In and Out parameter dialog boxes. Port location and speed are specified in the constraints file by IOB timing.
This topic describes how System Generator handles hardware clocks in the HDL it generates. Assume
the design is named <design>
, and <design>
is an acceptable HDL identifier. When System Generator compiles the design, it writes a
collection of HDL entities or modules, the topmost of which is named
<design>
, and is stored in a file named
<design>.vhd/.v
.