Block Parameters for the Ethernet Hardware Co-Simulation Block - 2020.2 English

Vivado Design Suite User Guide: Model-Based DSP Design Using System Generator (UG897)

Document ID
UG897
Release Date
2020-11-18
Version
2020.2 English

The block parameters dialog box for the Ethernet hardware co-simulation block can be invoked by double-clicking the block icon in your Simulink model.

Parameters specific to the block are as follows:

Basic tab

Clocking

Clock source
Specifies the clocking mode (Single stepped or Free running) used to synchronize the System Generator hardware co-simulation block with its associated FPGA or SoC hardware. For a description of the two clock sources, see Clocking Modes.

Has combinational path: Select this if your circuit has any combinational paths. A combinational path is one in which a change propagates from input to output without any clock event. There is no sequential logic (latches, flip-flops, or registers) in the path. Enabling this option causes System Generator to read the outputs immediately after writing inputs, before clocking the design. This ensures that value changes on combinational paths extending from the hardware co-simulation block into the Simulink model get propagated correctly.

Bitstream file: Specify the FPGA configuration bitstream. By default this field contains the path to the bitstream generated by System Generator during the last Generate triggered from the System Generator token.

Advanced tab

Skip device configuration: When selected, the configuration bitstream will not be loaded into the FPGA or SoC. This option can be used if another program is configuring the device (for example, the Vivado Hardware Manager and the Vivado Logic Analyzer).

Display Part Information: This option toggles the display of the device part information string (for example, xc7k325tffg900-2 for a Kintex device) in the center of the hardware co-simulation block.

Ethernet tab

Host Interface

Ethernet Interface: This drop-down list contains all the Ethernet interfaces detected in the host computer. Select the interface which is connected to the target board. The selected interface must be configured correctly to perform the Point-to-Point Ethernet hardware co-simulation. For a description of the host interface configuration, see Setting Up the Local Area Network on the PC.

Refresh button: the Refresh button gives you the ability to re-enumerate the available Ethernet interfaces. The button can be used to display Ethernet interfaces that can be hot-plugged (for example, USB-to-Ethernet adapters) or interfaces that are disabled when you open the block parameters dialog box but are enabled afterwards.

FPGA Interface

MAC Address: This is the Ethernet MAC address assigned to the target board. If left blank, the default value is da:02:03:04:05:06. This value should never be the same as the host's MAC address.

Configuration tab

Cable

Type
Currently, Auto Detect is the only setting for this parameter. System Generator will automatically detect the cable type.

Configuration timeout (ms): Specify the timeout value for the initial Ethernet handshake after configuration.