Bidirectional ports (or inout ports) are supported only during the generation of
the HDL netlist, that is, bi-directional ports will not show up in the System Generator diagram. By default, bi-directional ports will be driven with 'X'
during simulation. It is possible to overwrite this behavior by associating a data file to the
port. Be sure to guard this code because bi-directional ports can only be added to a block
during the config_netlist_interface phase.
if (strcmpi(this_block.getConfigPhaseString,'config_netlist_interface'))
bidi_port = this_block.port('bidi');
bidi_port.setGatewayFileName('bidi.dat');
end
In the above example, a text file, bidi.dat, is used during
simulation to provide stimulation to the port. The data file should be a text file, where each
line represents the signal driven on the port at each simulation cycle. For example, a 3-bit
bi-directional port that is simulated for 4 cycles might have the following data file:
ZZZ
110
011
XXX
Simulation will return with an error if the specified data file cannot be found.