Sometimes it is important to add one or more existing HDL modules to a System Generator design.
The System Generator Black Box
block allows VHDL, and Verilog, to be brought into a design.
The Black Box block behaves like other System Generator blocks - it is wired into
the design, participates in simulations, and is compiled into
hardware. When System Generator compiles a Black Box block, it automatically connects the
ports of the Black Box to the rest of the design. A Black Box
can be configured to support either synchronous clock designs or
multiple hardware clock designs based on the context and
System Generator
token settings.