Known Issues - 2020.2 English

Vivado Design Suite User Guide: Model-Based DSP Design Using System Generator (UG897)

Document ID
UG897
Release Date
2020-11-18
Version
2020.2 English

The following are some of the known issues:

  • The HWCosim Compilation Target is not supported for Multiple Clock Designs.
  • Only FIFO & Dual Port RAM blocks can be in the top-level of the design when using multiple clocks.
  • The behavior of blocks that aid in the crossing of Multiple clock domains is NOT cycle accurate.
  • Unconnected or terminated output ports cannot be viewed in the Waveform Viewer.