System Generator extends Simulink to enable hardware design, providing high-level abstractions that can be automatically compiled into an FPGA. Although the arithmetic abstractions are suitable to Simulink (discrete time and space dynamical system simulation), System Generator also provides access to features in the underlying FPGA.
The more you know about a hardware realization (e.g., how to exploit parallelism and pipelining), the better the implementation you’ll obtain. Using IP cores makes it possible to have efficient FPGA designs that include complex functions like FFTs. System Generator also makes it possible to refine a model to more accurately fit the application.
Scattered throughout the System Generator documentation are notes that explain ways in which system parameters can be used to exploit hardware capabilities.