Burst Data Transfers for Hardware Co-Simulation - 2020.2 English

Vivado Design Suite User Guide: Model-Based DSP Design Using System Generator (UG897)

Document ID
UG897
Release Date
2020-11-18
Version
2020.2 English

Hardware co-simulation (HWCosim) is a methodology by which a user can offload, either partially or whole, the most compute intensive portion of a model into the actual target FPGA platform. The host system provides the stimulus to the model via the co-simulation interface (typically JTAG and/or point-to-point Ethernet) and post-processes the response. This methodology is useful for validating the correctness of the generated hardware design on the target platform itself, as well as for speeding up the simulation time during verification of the model in a hardware co-verification scenario.

MATLAB/Simulink in conjunction with System Generator for DSP currently supports two variants of HWCosim: GUI-based and MATLAB M-script based. The first is run under the control of the Simulink scheduler, and can only progress one clock cycle at a time, due to the potential for feedback loops in the model.

The second variant is MATLAB M-script based simulation under System Generator control (M-HWCosim), which is commonly used in testbenches produced as collateral during the bitstream generation from the System Generator token. These testbenches are typically feedback-free and come with a-priori known input that can be transferred to the device in larger batches.

Previous generations of System Generator for DSP (Vivado) implemented only a basic variant of HWCosim, which did not harness the full performance potential of the interface. Command and response packets were sent in single-cycle batches, only utilizing a small part of the available bandwidth. This leaves a lot of performance on the table which the latest version of System Generator for DSP aims to reclaim.