| setTopLevelLanguage(language) |
Declares language for the top-level entity (or module) of the black box. The language should
be VHDL or Verilog. |
| setEntityName(name) |
Sets name of the entity or module. |
| addSimulinkInport(pname) |
Adds an input port to the black box. pname defines the name the port should have. |
| addSimulinkOutport(pname) |
Adds an output port to the black box. pname defines the name the port should have. |
| setSimulinkPorts(in,out) |
Adds input and output ports to the black box.
in (respectively, out) is a cell array whose element tell the names to
use for the input (resp., output) ports. |
| addInoutport(pname) |
Adds a bidirectional port to the black box. pname defines the name the port should have.
Bidirectional ports can only be added during the
config_netlist_interface phase of configuration. |
| tagAsCombinational() |
Indicate that the block has a combinational
path (i.e., direct feedthrough) from an input port to an output port. |
| addClkCEPair(clkPname, cePname, rate) |
Defines a clock/clock enable port pair for the
block. clkPname and cePname tell the names for the clock and clock enable
ports respectively. rate, a double, tells the rate at which the port
pair runs. The rate must be a positive integer. Note the clock (respectively,
clock enable) name must contain the substring clk (resp., ce). The names
must be parallel in the sense that the clock enable name is obtained
from the clock name by replacing clk with ce. |
| port(name) |
Returns the SysgenPortDescriptor that matches
the specified name. |
| inport(indx) |
Returns the SysgenPortDescriptor that describes
a given input port. indx tells the index of the port to look for, and
should be between 1 and numInputPorts. |
| outport(indx) |
Returns the SysgenPortDescriptor that describes
a given output port. indx tells the index of the port to look for, and
should be between 1 and numOutputPorts. |
| addGeneric(identifier, value) |
Defines a generic (or parameter if using Verilog) for the block. identifier is a string that
tells the name of the generic. value can be a double or a string. The
type of the generic is inferred from value's type. If value is an
integral double (e.g., 4.0), the type of the generic is set to integer.
For a non-integral double, the type is set to real. When value is a
string containing only zeros and ones (e.g., `0101'), the type is set to
bit_vector. For any other string value, the type is set to
string. |
| addGeneric(identifier, type, value) |
Explicitly specifies the name, type, and value for a generic (or parameter,
if using Verilog) for the block. All three
arguments are strings. identifier tells the name,
type tells the type, and value tells the
value. |
| addFile(fn) |
Adds a file name to the list of files associated to this black box,
fn is the file name. Ordinarily,
HDL files are associated to black boxes, but any
sorts of files are acceptable. VHDL file names
should end in .vhd; Verilog file
names should end in .v. The order
in which file names are added is preserved, and
becomes the order in which HDL files are compiled.
File names can be absolute or relative. Relative
file names are interpreted with respect to the
location of the .mdl or library .mdl for the
design. |
| getDeviceFamilyName() |
Gets the name of the FPGA corresponding to the black box. |
| getConfigPhaseString |
Returns the current configuration phase as a string. A valid return string
includes: config_interface, config_rate_and_type,
config_post_rate_and_type, config_simulation,
config_netlist_interface, and
config_netlist. |
| setSimulatorCompilationScript(script) |
Overrides the default HDL co-simulation compilation script that the black box
generates. script tells the name
of the script to use. For example, this method can
be used to short-circuit the compilation phase for
repeated simulations where the HDL for the black
box remains unchanged. |
| setError(message) |
Indicates that an error has occurred, and records the error message.
message gives the error
message. |