- Change the Source Design
- Use Additional Pipelining
Use the Output and Pipeline registers inside block RAM and DSP48s.
- Run Functions in Parallel
Run functions in parallel at a slower clock rate
- Use Retiming Techniques
Move existing registers through combinational logic.
- Use Hard Cores where Possible
Use Block RAM instead of distributed RAM.
- Use a Different Design Approach for Functions
- Use Additional Pipelining
- Avoid Over-Constraining the Design
Do not over-constrain the design and use up/down sample blocks where appropriate.
- Consider Decreasing the Frequency of Critical Design Modules
- Squeeze Out the Implementation Tools
- Try Different Synthesis Options.
- Floorplan Critical Modules