While the Super Sample Rate (SSR) feature introduced in this section can be widely applicable to all Xilinx® devices, this section explains the motivation for it for Xilinx RFSoC devices. The integration of direct RF-sampling data converters with Xilinx’s technology offers the most flexible, smallest footprint, and lowest power solution for a wide range of high performance RF applications such as Wireless communications, cable access, test & measurement, and radar. RFSoC devices provide hardened Digital Up Converters (DUC) and Digital Down Converters (DDC). NCO, Complex Mixers, and Filters are hard Macros, and filter characteristics are optimized for general Commercial applications.
Depending on what is needed, RFSoC devices can be used in two ways.
- Use the available hardened NCO & Complex Mix and Half Band Decimation/interpolation filters.
- If the sequence of the hardened blocks does not meet the design requirement, you can bypass them as shown in the figure above.
In the latter case, to meet the design requirements, you may need to implement the NCO, Complex Mixerm and DDC blocks in the fabric using System Generator for DSP. To do this, bypass the hardened blocks, and let System Generator IPs run at Programmable Logic (PL) clock frequency. When the sample rate from the ADC is in GSPS, and PL handles only the MSPS range of data, you must accept and compute multiple parallel samples every clock cycle for each data channel. The number of parallel samples is determined by calculating the ratio between the sample frequency and the Programmable Logic clock frequency, which is defined as an SSR parameter.
What is SSR?
SSR is a parameter that determines how many parallel samples to accept for every clock cycle.
How SSR helps users?
- SSR is beneficial for users who cannot use the hardened RFSoC DUC and DDCs.
- SSR provides programmatic subsystems for NCO and Complex Mixer among many others. The user input parameters in the block mask and System Generator programmatically construct the underlying subsystem with multiple DDS blocks.
- SSR avoids manual and structural modifications to your design, which accelerates the design-cycle.
SSR Library
System Generator provides a separate set of library blocks for handling SSR. Currently, System Generator supports 25 vector blocks, which can be accessed from the MATLAB® Library Browser.
The SSR parameter can be defined for all the blocks present in the SSR block set. When you add a block from the library, the default SSR value is 4, and the maximum SSR valiue is 256.
The SSR block set is defined in Vivado Design Suite Reference Guide: Model-Based DSP Design Using System Generator (UG958).
No matter what the SSR rate is, you only need to provide a limited number of signal connections as with a normal IP block. System Generator automatically takes care of all the parallel path connection internal to the SSR block, according to the SSR parameter value provided.
For example, for a Vector AddSub block, when SSR parameter is modified to 3, the internal connections are done automatically as shown below. This creates 3 parallel paths for computation and results in single output.