How to Use - 2020.2 English

Vivado Design Suite User Guide: Model-Based DSP Design Using System Generator (UG897)

Document ID
UG897
Release Date
2020-11-18
Version
2020.2 English

Terminating Open Outputs

Consider the following model with open input and output ports:

Figure 1. Model with Open Input and Output Ports

Right-click the DDS Compiler 5.0 block in this case and select Xilinx Tools > Terminate > Outputs.

The following figure illustrates the resulting terminated outputs.

Figure 2. Terminated Output Ports

Terminating Open Inputs

Consider the following model with an open input port:

Figure 3. Model with Open Input Port

Right-click the DDS Compiler 5.0 block and select:

Xilinx Tools > Terminate > Inputs

The following figure illustrates the resulting terminated input.

Figure 4. Terminated Input Port