Many of the XPLL ports are identical to those for the MMCM (see MMCM Port Descriptions). For dynamic reconfiguration port description, see Dynamic Reconfiguration Port (DRP). The additional ports available for the XPLL are described in this section.
- CLKOUTPHY and CLKOUTPHYEN
- The XPLL provides a dedicated CLKOUTPHY clock output to the XPHY. There is
special logic associated with this clock output to support the synchronization
between the programmable logic clock and the XPHY clock generated by the VCO.
CLKOUTPHY is gated by the CLKOUTPHYEN signal from the programmable logic. When
the CLKOUTPHYEN signal is asserted High from the programmable logic, CLKOUTPHY
starts toggling so that the rising edge is aligned with the rising edge of the
XPLL input clock. To ensure CLKOUTPHY is aligned with the clock that drives data
to XPHY nibbles in an XPIO bank, the data clock has to be the same clock as the
XPLL input clock. The CLKOUTPHYEN signal is synchronized to a divide by 8 clock
dividers and gates the CLKOUTPHY clock. CLKOUTx_DIVIDE and CLKOUT_MULT are
synchronized to the internal clock. However, phase alignment between multiple
XPLL CLKOUTPHY clocks is only ensured when both the CLKFBOUT_MULT and
CLKOUT[0:1]_DIVIDE values are set to 1, 2, 4, 8, and 16. Rising edges do not
align for CLKFBOUT = 3, 5, 6, 7, 9,… The following figure shows how clock
division and multiplexing is achieved for enabling the CLKOUTPHY clock based on
the CLKOUTPHYEN signal and CLKOUTPHY_DIVIDE attribute.Figure 1. CLKOUTPHY Multiplexer Scheme
- XPHY RIU interface pins
- These pins provide a direct connection to the hardened memory controller for highest performance deterministic timing.