BUFGMUX and BUFGMUX_1

Versal Adaptive SoC Clocking Resources Architecture Manual (AM003)
Document ID
AM003
Release Date
2023-05-16
Revision
1.5 English

BUFGMUX is a clock buffer with two clock inputs, one clock output, and a select line. This primitive is based on BUFGCTRL with some pins connected to logic High or Low. The following figure illustrates the relationship of BUFGMUX and BUFGCTRL. The LOC constraint is available for manually placing the BUFGMUX and BUFGCTRL locations. See the Vivado Design Suite User Guide: Using Constraints (UG903) for more information.

Figure 1. BUFGMUX using BUFGCTRL
Important: When using the select, the setup time requirement must be met because BUFGMUX uses the CE pins as select pins. Violating this setup time can result in a glitch.

Switching conditions for BUFGMUX are the same as the CE pins on BUFGCTRL. The following figure illustrates the timing diagram for BUFGMUX.

Figure 2. BUFGMUX Timing Diagram
The figure shows:
  • The current clock is I0
  • S is activated High
  • If I0 is currently High, the multiplexer waits for I0 to deassert Low
  • After I0 is Low, the multiplexer output stays Low until I1 transitions from High to Low
  • When I1 transitions from High to Low, the output switches to I1
  • If setup/hold times are met, no glitches or short pulses can appear on the output

BUFGMUX_1 is rising-edge sensitive and held at High prior to input switch. The following figure illustrates the timing diagram for BUFGMUX_1. The LOC constraint is available for manually placing the BUFGMUX and BUFGMUX_1 locations. See the Vivado Design Suite User Guide: Using Constraints (UG903) for more information.

Figure 3. BUFGMUX_1 Timing Diagram
The figure shows:
  • The current clock is I0
  • S is activated High
  • If I0 is currently Low, the multiplexer waits for I0 to be asserted High
  • After I0 is High, the multiplexer output stays High until I1 transitions from Low to High
  • When I1 transitions from Low to High, the output switches to I1
  • If setup/hold times are met, no glitches or short pulses can appear on the output

The following table summarizes the attributes for the BUFGMUX primitive.

Table 1. BUFGMUX Attributes
Attribute Name Description Possible Values
CLK_SEL_TYPE Specifies synchronous or asynchronous clock switching. SYNC (default), ASYNC