MMCM Ports

Versal Adaptive SoC Clocking Resources Architecture Manual (AM003)

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The following table summarizes the MMCM ports.

Table 1. MMCM Ports
Port Name I/O Description
CLKIN1 Input General clock input.
CLKIN2 Input Secondary clock input for the MMCM reference clock.
CLKFBIN Input Feedback clock input.
CLKINSEL Input This signal controls the state of the clock input MUX, High = CLKIN1, and Low = CLKIN2. CLKINSEL dynamically switches the MMCM reference clock.
CLKOUT[0:6] Output User configurable clock outputs (0 through 6) that can be divided versions of the VCO phase outputs (user controllable) from 2 to 512. The output clocks are phase aligned to each other (unless phase shifted) and aligned to the input clock with a proper feedback configuration.
CLKFBOUT Output Dedicated MMCM feedback output.
CLKINSTOPPED Output Status pin indicating that the input clock has stopped.
CLKIN1_DESKEW Input Primary clock input to the phase detector 1 block for deskewing clock network delays between two different CLKOUT networks.
CLKFB1_DESKEW Input Secondary (feedback) clock input to the phase detector1 block for deskewing clock network delays.
CLKIN2_DESKEW Input Primary clock input to the phase detector 2 block for deskewing clock network delays between two different CLKOUT networks.
CLKFB2_DESKEW Input Secondary (feedback) clock input to the phase detector2 block for deskewing clock network delays.
CLKFBSTOPPED Output Status pin indicating that the feedback clock has stopped.
DADDR[6:0] Input The dynamic reconfiguration address (DADDR) input bus provides a reconfiguration address for the dynamic reconfiguration. When not used, all bits must be assigned zeros.
DI[15:0] Input The dynamic reconfiguration data input (DI) bus provides reconfiguration data. When not used, all bits must be set to zero.
DO[15:0] Output The dynamic reconfiguration output bus provides MMCM data output when using dynamic reconfiguration.
DRDY Output The dynamic reconfiguration ready output (DRDY) provides the response to the DEN signal for the MMCM’s dynamic reconfiguration feature.
DWE Input The dynamic reconfiguration write enable (DWE) input pin provides the write enable control signal to write the DI data into the DADDR address. When not used, it must be tied Low.
DEN Input The dynamic reconfiguration enable (DEN) provides the enable control signal to access the dynamic reconfiguration feature. When the dynamic reconfiguration feature is not used, DEN must be tied Low.
DCLK Input The DCLK signal is the reference clock for the dynamic reconfiguration port.
LOCKED Output The LOCKED signal indicates that all functions requiring a LOCKED signal for the MMCM to operate properly have LOCKED. This LOCKED signal is therefore an AND function of LOCKED_FB and both LOCKED1/2_DESKEWs, if used.
LOCKED_FB Output An output from the MMCM that indicates when the MMCM has achieved phase alignment within a predefined window and frequency matching within a predefined PPM range. The MMCM automatically locks after power on. No extra reset is required. LOCKED is deasserted if the input clock stops or the phase alignment is violated (for example, input clock phase shift). The MMCM must be reset after LOCKED is deasserted.
LOCKED1/2_DESKEW Output Indicates if the deskew circuit is locked. Applies only to the deskew circuits used in the design. Ignore these outputs for unused deskew circuits.
PSCLK Input Phase shift clock.
PSEN Input Phase shift enable.
PSINCDEC Input Phase shift increment/decrement control.
PSDONE Output Phase shift done.
RST Input Asynchronous reset signal. The RST signal is an asynchronous reset for the MMCM. The MMCM synchronously re-enables itself when this signal is released (that is, MMCM re-enabled). A reset is required when the input clock conditions change (for example, frequency).
PWRDWN Input Powers down instantiated but unused MMCMs.
  1. All control and status signals except PSINCDEC are active-High.
  2. See the Dynamic Reconfiguration Port (DRP) section for further information and recommendations on dynamic reconfiguration ports.
Tip: The port names generated by the clocking wizard can differ from the port names used on the primitive.