Clocking Resources Features

Versal Adaptive SoC Clocking Resources Architecture Manual (AM003)

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1.5 English

Versal architecture clocking resources manage complex and simple clocking requirements with dedicated global clocks distributed on clock routing and clock distribution resources. The global clocking network in Versal architecture is largely similar in structure to the AMD UltraScale™ families. It is a bidirectional, segmented network of clock spines that support many independent clock networks, and allows the same structure to be used for low skew or low propagation clocks.

Most departures from the UltraScale clocking architecture are related to skew and jitter minimization implementation strategies that leave the base architecture intact. The clock management functions (MMCMs, XPLLs, and DPLLs) provide clock frequency synthesis, deskew, and jitter filtering functionality. Non-clock resources such as local routing are not recommended when designing for clock functions.

  • The core of the device is subdivided into columns and rows of segmented clock regions (CRs). CRs are arranged in tiles. A CR contains configurable logic blocks (CLBs), DSP Engine, block RAMs, UltraRAMs, interconnect, and associated clocking. Gigabit transceivers (Type Y or M) are placed in the right and left most columns. In the lower left side resides the Arm® based processor system (PS) which also contains a platform management controller (PMC) that manages the overall system such as configuration, health-monitoring (root SYSMON), security, and various other tasks. In some devices, an interconnect for CCIX and PCIe® (CPM) sits on top of the PS+PMC block. Other hard block IPs such as PCIe, Interlaken (ILKN), 100G multirate Ethernet MAC (MRMAC), 600G Ethernet MAC (DCMAC), forward error correction (SD-FEC), and high-density I/Os (HDIOs) are arranged in a separate vertical hardblock IP columns. To support the network on a chip (NoC) concept horizontal NoC columns run on top and bottom of the core and vertical NoC columns are embedded in the core in regular intervals. The top or bottom of the core can have high-performance I/Os (XPIOs) or AI Engine on top only. Hard memory controllers are also located along with the XPIOs in the bottom. The mixture of the above features varies with Versal devices.
  • Unlike the previous two generations, Versal devices implement full and half CRs. The height of a full CR is 96 CLBs, 48 DSP58s, typically 24 block RAMs, and 24 UltraRAMs with a horizontal clock spine (HCS) at its center. A half CR is half the height of a full CR and the HCS run in the bottom. The HCS contains the horizontal routing and distribution resources, leaf clock buffers, and clock network interconnections. Clock buffers drive into the HCS. If present, there are two banks of 22 HDIO each per CR in the HDIO.
  • Vertical logic clock columns exist on the programmable logic (PL) interior. A CR is bound by vertical routing on one side and a BRAM column on the other. CRs are placed back-to-back with a vertical clocking column in between each pair. GT clocking columns are next to the GTs. The HCSs are in their traditional location in the center of each CR spanning the entire programmable logic region except in the half CR where they are at the bottom of the CR. The clocking drives vertical and horizontal connectivity through separate clock routing and clock distribution resources through the HCS.
  • Two XPLLs are embedded in the center of each XPIO bank and directly connect to XPHY logic/XPIO and the horizontal clock row, thus driving the BUFG resources. XPLLs can be cascaded through a direct connection to support wider interfaces.
  • DPLLs are located to the left and right of the GT clock columns. In devices with HDIO columns, DPLLs are also located next to those I/O columns.
  • Mixed-mode clock managers (MMCMs) are located adjacent to the XPIO banks in a horizontal clock row with the various clock BUFG buffers such as BUFGCE, BUFGCTRL, and BUFGCE_DIV next to them. Each MMCM site also incorporates a DPLL next to it increasing the total MMCM equivalent count.
  • BUFG_GTs reside in the same clock columns next to the GT block and drive horizontal and vertical clock routing.
  • BUFG_PSs reside in the clock region next to the PS/PMC block and can drive vertical and horizontal clocking.
  • Horizontal clock routing and distribution tracks drive horizontally into the CRs. Vertical routing and distribution tracks drive vertically adjacent CRs. The tracks are segmentable at the CR boundaries in both the horizontal and vertical directions. This allows for the creation of device-wide global clocks or local clocks of variable size.
  • The distribution tracks drive the clocking of synchronous elements across the device. Distribution tracks are driven by routing tracks or directly by the clocking structures in the PHY.
  • Versal architecture clock input pins drive XPLLs, BUFGs, DPLLs, and MMCMs.
Figure 1. High-Level Architecture View
Terms used in the previous figure:
Network on chip.
Physical connection between GTY and PCIe® in the CPM block.
High-density I/O and high performance I/O.
100GE MAC and PCS.
Interconnect for CCIX and PCIe features of the PS subsystem.
Cache Coherent Interconnect for Accelerators.
Interlaken Hard-IP block.
100G multirate Ethernet MAC and PCS.
600G Ethernet MAC and PCS.
Software defined forward error correction.
Fabric super region: a collection of cores that make up repeatable blocks in the PL region and represent a CR.
Horizontal super region: a row of NoC clocking and system monitor circuits located adjacent to the I/O. The width of the HSR matches that of an I/O bank.