Versal Adaptive SoC Clocking Resources Architecture Manual (AM003)

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The MMCMs serve as frequency synthesizers for a wide range of frequencies, and as jitter filters for either external or internal clocks, and deskew clocks.

The clock input connectivity allows multiple resources to provide the reference clock(s) to the MMCM. The number of output counters (dividers) is seven. MMCMs have 32 step phase interpolators feeding the input of the output and feedback counters thus providing infinite fine phase shift capability in either direction and can be used in dynamic phase shift mode. The resolution of the fine phase shift is 1/32 of the VCO frequency. In addition to integer divide output counters, MMCMs can support fractional feedback divide values using a sigma-delta module (SDM). This effectively allows for a clock multiplier to be specified with a resolution of 1/(26) (6 bits) to support greater clock frequency synthesis capability than before. The new fractional divide support is available on CLKFBOUT counter M. CLKOUT0 no longer has separate fractional divide.

MMCMs also have the capability to generate spread-spectrum clocks that vary the clock frequency very slowly to spread the clock’s electromagnetic (EM) energy over a frequency band. This reduces the maximum EM energy at any single frequency. If the MMCM spread-spectrum feature is not used, a spread spectrum on an external input clock is not filtered and thus passed on to the output clock.

Input multiplexers select the reference and feedback clocks from either the global clock I/Os or the clock routing or distribution routing resources. Each clock input has a programmable divider (D). The phase-frequency detector (PFD) compares both phase and frequency of the rising edges of both the input (reference) clock and the feedback clock. If a minimum high/low pulse is maintained, the duty cycle is ancillary. The PFD is used to generate a signal proportional to the phase and frequency between the two clocks. This signal drives the charge pump (CP) and loop filter (LF) to generate a reference voltage to the VCO. The PFD produces an up or down signal to the charge pump and loop filter to determine whether the VCO should operate at a higher or lower frequency. When VCO operates at a frequency that is too high, the PFD activates a down signal causing the control voltage to be reduced, thus decreasing the VCO operating frequency. When the VCO operates at a frequency that is too low, an up signal increases the voltage. The VCO produces eight 45 degree output phases which in turn feed the eight PIs. The PI can convert the 8 VCO phases into 32 VCO phases. Each PI output is then fed to a corresponding counter (O or M counters). Each output phase can be selected as the reference clock to the counters (see the following figure). Each counter can be independently programmed for a given customer design. A special counter M is also provided. This counter controls the feedback clock of the MMCM, allowing a wide range of frequency synthesis.

A deskew sub-block consists of two deskew phase detectors (PDs) and phase interpolators (PIs). Each of the PIs can be controlled either by one of the two deskew PDs or by the phase shift interface. Each deskew PD takes in two clock inputs, CLKIN1_DESKEW/CLKIN2_DESKEW and CLKFB1_DESKEW/CLKFB2_DESKEW and adjusts the PIs controlled by the deskew network to drive the delay between the rising edges of the two clocks to zero. For more information about requirements on the sets of clock inputs, see Functioning of Deskew.

Important: The MMCM/XPLL/DPLL output clocks using this deskew scheme are not phase aligned to the other output clocks.

A phase shift interface system is also present. The PIs can be chosen to be controlled by nothing (not used), either of the two deskew PDs, or by the phase shift interface. Using this interface, the PIs under the control of phase shift interface can be incremented or decremented by 1-step dynamically while the MMCM is locked and operational. This includes the feedback PI (PIFB).

Figure 1. MMCM Block Diagram