Revision History

The following table shows the revision history for this document.

Section	Revision Summary
05/16/2023 Version 1.5
Clocking Resources Features	Revised Figure 1 and terms to include FSR and HSR.
Clock Management MMCM, XPLL, and DPLL	Revised Figure 1 and added SSI technology device figure.
Global Clock Inputs	Revised GC pin connection to include non-adjacent banks.
Clock Buffers	Added a description of the clock tree span impact on the global clock Fmax.
Clock Skew Minimization through Calibrated Mesh Network Deskew	Revised note.
Clock Buffer Resources	Revised the clock description in the XPIO bank.
Multi-Clock Buffers	Revised the description of MBUFGCE_DIV.
Overview	Added description of devices with top clock regions.
05/24/2022 Version 1.4
Differences from Previous Generations and DPLLs	Removed information on the DPLL not having fractional clock generation capabilities.
Clock Skew Minimization through Calibrated Mesh Network Deskew	Revised adaptive deskew information.
Multi-Clock Buffers	Updated MBUFG-type clock buffer output usage.
Detailed VCO and Output Counter Waveforms	Removed statement that O0 can be used in fractional divide mode.
Using Fractional Divide	Added information on the limitation of VCO frequency on jitter performance.
Safe Timing Requirements for Multiple PLL and Clock Buffer Configuration	New section.
Limitations	Removed duty cycle programmability.
DPLL Attributes	Updated DPLL PERF_MODE attribute description.
Limitations	Removed duty cycle programmability.
XPLL Port Descriptions	Added requirement for CLKOUTPHY to be in phase with the XPHY data clock. Updated CLKOUTPHYEN related details.
12/17/2021 Version 1.3
Clock Skew Minimization through Calibrated Mesh Network Deskew	Added a note to specify the status of calibrated deskew setting.
BUFGCE_DIV	Removed ASYNC from BUFGCE_DIV CE_TYPE attribute description.
Multi-Clock Buffers	Added information about MBUFG type clock buffer usage. Added description to output for MBUG_GT and MBUFGCE_DIV.
Using the Deskew Logic	Removed recommendation using digital deskew for feedback that is going outside device.
Duty Cycle Programmability	Added information about duty cycle programmability in deskew and non-deskew mode.
MMCM Port Descriptions	Updated CLKIN1 and CLKFBIN descriptions.
MMCM Attributes	Corrected DESKEW_DELAY_PATH1/2 in MMCM attribute table. If TRUE, the corresponding CLKFBx_DESKEW path should be selected.
Functioning of Deskew	Updated digital deskew guidelines.
Safe Timing Clocking Topologies for MMCM and XPLL	New section.
Phase Align Selected Clock Outputs of Two MMCMs	Updated figure.
Phase Align Selected Clocks in Different Versal Devices	Updated figure.
Safe Timing Clocking Topologies for DPLL	New section.
DPLL Attributes	Removed the CLKOUT[0:3]_DUTY_CYCLE attribute.
XPLL Attributes	Corrected DESKEW_DELAY_PATH1/2 in XPLL attribute table. If TRUE, the corresponding CLKFBx_DESKEW path should be selected.
XPLL Cascade	New section.
Clock Jitter Due to Memory Resource Activity	New appendix.
04/23/2021 Version 1.2
Differences from Previous Generations	Updated to specify that automatic migration from MMCM_ADV to MMCME5 is not supported. Added information about clock jitter due to memory resource activity.
MMCM Attributes	Added static phase shift increments for CLKOUT[0:6]_PHASE attributes.
Static Phase Shift Mode Using Counters and VCO Phases (MMCM and XPLL) or DCO Phases (DPLL)	Updated minimum phase resolution (ps) equation.
DPLL Attributes	Added attribute PERF_MODE, as well as static phase shift increments for CLKOUT[0:3]_PHASE attributes.
XPLL Attributes	Added static phase shift increments for CLKOUT[0:3]_PHASE attributes.
12/07/2020 Version 1.1
Clocking Resources Features	Updated to add information about RAMs in a full clock region, as well as updated figure to remove CMAC.
Differences from Previous Generations	Updated deskew description for XPLL.
Using the Deskew Logic	Added details about using digital skew with external clock network delay.
Limitations	Added device specific limitations for the DPLL.
Deskew Logic - Additional Deskew Options	Clarified description.
Functioning of Deskew	Added requirements related to clock input source.
Phase Align Selected Clocks in Different Versal Devices	Added clock input requirements.
07/16/2020 Version 1.0
Initial release.	N/A