Clock Buffer Resources

Versal Adaptive SoC Clocking Resources Architecture Manual (AM003)

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Clock buffers are near their intended clock sources. Next to the XPIO, XPHY global clocking contains several sets of BUFGCTRLs, BUFGCEs, and BUFGCE_DIVs. Each set can be driven by four GC pins from the XPIO bank, MMCMs, XPLLs, and DPLLs in the bottom of the part, and interconnect. Four BUFGs next to the HDIO columns can be driven by two GC pins. The clock buffers then drive the routing and distribution resources across the entire device. Each XPIO clocking block contains 24 BUFGCEs, 8 BUFGCTRLs, and 4 BUFGCE_DIVs. Only 24 BUFGs in one XPIO clock region can be used to drive programmable logic (PL) clock loads or a mix of PL and XPIO clock loads. In the XPIO clock region, up to 12 unique clocks for XPIO I/O logic can be used, with up to 6 clocks available per half bank. The XPIO bank is made up of 9 XPHY nibbles, with XPHY0..3 on one side and XPHY4..8 on the other. See the Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010) for more information on the AMD Versal™ XPIO bank structure. HDIO clocking block only contains BUFGCEs. The BUFG_GTs can drive on horizontal routing to get to vertical routing in another column or drive the vertical routing in its own column directly.

In Versal architecture, BUFGCTRL multiplexers and all derivatives can be cascaded to adjacent clock buffers to create larger multiplexers. This feature can be used to create a ring of eight BUFGMUXes (BUFGCTRL multiplexers). For example, BUFGCTRL1 is fed by and feeds BUFGCTRL0 as well as BUFGCTRL2. This wraps around in such a way that BUFGCTRL0 is fed by and feeds BUFGCTRL7 as well as BUFGCTRL1.

The following figure shows a simplified diagram of cascading BUFGCTRLs.

Figure 1. BUFGCTRL Cascading

The following subsections detail the various configurations, primitives, and use models of the clock buffers.