| Attribute | Type | Allowed Values | Default | Description |
|---|---|---|---|---|
| CLKOUT[0:3]_DIVIDE | Integer | 2 to 128 | 2 | Specifies the amount to divide the associated CLKOUT clock output if a different frequency is desired. This number, in combination with the CLKFBOUT_MULT values, determines the output frequency. |
| CLKOUT[0:3]_ DUTY_CYCLE | Real | 0.001 to 0.999 | 0.50 | Specifies the duty cycle of the associated CLKOUT clock output in percentages (that is, 0.50 generates a 50% duty cycle). |
| CLKFBOUT_MULT | Decimal | 4 to 43 | 42 | Specifies the amount to multiply all CLKOUT clock outputs if a different frequency is desired. This number, in combination with the associated CLKOUT#_DIVIDE value and DIVCLK_DIVIDE value, determines the output frequency. |
| CLKOUT[0:3]_PHASE | Real | –360.000 to 360.000 | 0.000 | Allows specification of the output phase relationship of the associated CLKOUT clock output in number of degrees offset (that is, 90 indicates a 90° offset or ¼ cycle phase offset while 180 indicates a 180° offset or ½ cycle phase offset). In static phase shift mode, the minimum phase step resolution (degrees) = (360/CLKOUT[0:3]_DIVIDE)/8. |
| DIVCLK_DIVIDE | Decimal | 1 to 12 | 1 | Specifies the division ratio for all output clocks with respect to the input clock. |
| REF_JITTER | Real | 0.000 to 0.200 | 0.010 | Allows specification of the expected jitter on the reference clock to better optimize PLL performance. A bandwidth setting of OPTIMIZED attempts to choose the best parameter for input clocking when unknown. If known, the value provided should be specified in terms of the unit interval (UI) (the maximum peak-to-peak value) of the expected jitter on the input clock. |
| CLKIN_PERIOD | Real | 0.000 to 100.000 | 0.000 | Specifies the input period in ns to the PLL CLKIN input. Resolution is down to the ps. This information is mandatory and must be supplied. |
| CLKOUTn_PHASE_CTRL[0:1] | Binary | 00 to 11 | 00 |
CLKFBOUT counter variable fine phase shift or deskew select. 00: Interpolator is not controlled by either deskew or phase shift interface. 01: Interpolator is controlled by deskew1. 10: Interpolator is controlled by phase shift interface. 11: Interpolator is controlled by deskew2. |
| DESKEW_DELAY1 | Decimal | 0 to 63 | 0 | Value of the optional programmable delay in the deskew1 circuit. |
| DESKEW_DELAY2 | Decimal | 0 to 63 | 0 | Value of the optional programmable delay in the deskew2 circuit. |
| DESKEW_DELAY_PATH1 | String | TRUE, FALSE | FALSE | Determines if the CLKIN1_DESKEW path or the CLKFB1_DESKEW path is selected for the optional programmable delay. TRUE = CLKFB1_DESKEW, FALSE = CLKIN1_DESKEW. |
| DESKEW_DELAY_PATH2 | String | TRUE, FALSE | FALSE | Determines if the CLKIN2_DESKEW path or the CLKFB2_DESKEW path is selected for the optional programmable delay. TRUE = CLKFB2_DESKEW, FALSE = CLKIN2_DESKEW. |
| DESKEW_DELAY_EN1 | String | FALSE, TRUE | FALSE | Set to TRUE to enable the optional programmable delay in the deskew circuit 1. |
| DESKEW_DELAY_EN2 | String | FALSE, TRUE | FALSE | Set to TRUE to enable the optional programmable delay in the deskew circuit 2. |
| CLKOUTPHY_DIVIDE | String | DIV1 (bypass), DIV2, DIV4, DIV8, DIV16 | DIV8 | Determines the CLKOUTPHYP and CLKOUTPHYN clocks by the VCO output clock. |
| LOCK_WAIT | String | FALSE, TRUE | FALSE | Wait during the configuration startup for the XPLL to lock. |
| XPLL_CONNECT_TO_NOCMC | String | NONE, LP4, DDR | NONE | Indicates if XPLL is used to drive the DDRMC. |