Functioning of Deskew

Versal Adaptive SoC Clocking Resources Architecture Manual (AM003)

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Figure 1. Example of an MMCM Using DESKEW for a Single Clock Output

  1. Apply a clock of any frequency, obeying the min/max values provided in the Versal adaptive SoC data sheets listed in References, to one of the clock inputs on an MMCM (3). The single clock is connected to both clock inputs and the CLKINSEL input being high determines that CLKIN1 is going to be used.
  2. Apply clock with the same frequency as CLKFB*_DESKEW, the input clock used for the feedback from CLKOUT, to the CLKIN*_DESKEW input (2). If both clocks are coming from CLKOUTs of the same PLL and have the same frequency, they are guaranteed to have no PPM difference because both CLKOUTs are derived from the same VCO.
  3. Route the required feedback network between CLKFBOUT (4) and CLKFBIN (7).
  4. M and D values are calculated to make the VCO run at the maximal possible frequency. The M value ensures the feedback counter runs at the same frequency as the MMCM input clock (CLKIN1), and that the following equation is fulfilled: Fin/D = Ffb = Fvco/M. One of the 32, 1-of-8 to after PI 1-of-32, output phases of the VCO is chosen as input clock for the output counter creating in this setup CLKOUT4. That counter divides the VCO clock down to the by CLKOUT4 required clock frequency.
  5. CLKOUT4 of the MMCM must be fed to a clock buffer (BUFG or its variant) to make sure the clock is distributed over the dedicated clock routing in the programmable logic. In this setup, the clock output (6), after passing through the clock buffer, is also routed back to a CLKFB_DESKEW input (8). One must make sure that the frequency calculated and generated by CLKOUT4 equals the frequency of the clock applied to the CLKINx_DESKEW pin as stated in point 2. The duty cycles of the two clocks are not required to be the same provided they are within specifications.
  6. In the normal operation mode of the MMCM, the phase frequency detector (PFD) block will make sure that the input clock (3) will be matched to the feedback clock (7) to make sure that the output clocks are deskewed and in phase with the MMCM input clock.
  7. In this example, the DESKEW logic is used and that is going to take precedence over the normal phase alignment. In this case, CLKOUT4 (6) is going to be aligned to the clock applied to CLKIN_DESKEW (2).
    1. This PD of the DESKEW circuit somewhat functions as the regular PFD circuit. Except that it does not alter the VCO frequency and selects with the phase interpolator (PI) one clock out of 32 and uses that as clock input for an output counter.
    2. The CLKIN_DESKEW clock and CLKFB_DESKEW clock, both of the same frequency, are rising edge phase compared to each other. When the phase between both clocks is not equal a signal will influence a, during setup of the MMCM, selected PI. The PI block will select 1-of-32 clock phases of the VCO output (per 11.25 degrees) as input for the attached output counter. This way the clock output will move in one direction or another to phase align the MMCM output clock with the extra foreign clock. The comparison will be done again and, when necessary, the deskew PD will act again on the selected PI. All this operates dynamically and ensures that the output clock, in this case CLKOUT4, will stay phase aligned to the external applied clock.
    3. CLKOUT4 will not be phase-aligned to other output clocks of the MMCM and will not be in phase with the clock input of the MMCM, but will be phase-aligned to the clock applied to the CLKIN_DESKEW input.
  8. In MMCM and XPLL, CLKINx_DESKEW must be of the same clock frequency as the CLKOUTx connected to CLKFBx_DESKEW with no PPM (parts-per-million) difference. To ensure the condition, the CLKINx and CLKINx_DESKEW inputs must be referenced to the same source, such as a crystal. In DPLL, regardless of whether it is in ZHOLD mode, CLKINx_DESKEW must be connected to CLKIN input and not from any CLKOUT feedback.
  9. In general, CLKFB_DESKEW is fed back from any CLKOUT through a BUFG or its variant. In DPLL, the ZHOLD mode applies to all CLKOUTs. Refer to the DPLL Attributes section for a description of the ZHOLD attribute.
  10. Multiple outputs can have a phase control setting of 01 if they have the same CLKOUTx_DIVIDE setting. The same is true for a phase control setting of 11.
    1. The phase relationship between the outputs defined by CLKOUTx_PHASE will be maintained.
    2. Design rule checks (available in Vivado tools 2022.1) will prevent you from having multiple outputs with different CLKOUTx_DIVIDE settings. In this case you must set the CLKOUTx_PHASE_CTRL to 00 or 10 for the outputs that are not driving the CLKFBx_DESKEW input and have a different CLKOUTx_DIVIDE setting.
  11. To enable deskew using PDs, the CLKOUTx that drives the corresponding CLKFBx_DESKEW must have CLKOUTx_PHASE_CTRL set to 01 if it is connected to CLKFB1_DESKEW or 11 if it is connected to CLKFB2_DESKEW. The following figure illustrates the connections between CLKOUTx and CLKFBx_DESKEW and settings for CLKOUTx_PHASE_CTRL.
Note: The figure at the beginning of this section shows the connections for analog compensation and digital deskew. Both analog compensation and digital deskew must not be connected at the same time.
Figure 2. MMCM Deskew using PDs Connections and CLKOUTn_PHASE_CTRL Settings