Static Phase Shift Mode Using Counters and VCO Phases (MMCM and XPLL) or DCO Phases (DPLL)

Versal Adaptive SoC Clocking Resources Architecture Manual (AM003)

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The VCO can provide eight phase-shifted clocks at 45° each; thus always providing possible settings for 0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315° of phase shift. The higher the VCO frequency is, the smaller the phase shift resolution. Because of the distinct operating range of the VCO, it is possible to bound the phase shift resolution using from (1/8Fvcomin) to (1/8Fvcomax) ps.

Note: Due to the phase interpolator (PI) in front of every counter, the output and feedback counters can operate on increments of 1/32nd of the VCO period. This applies to the static phase shift in Versal devices.

To achieve static phase shift between outputs of the dividers O0-O6 and feedback counter M for MMCM and XPLL or outputs of the dividers O0-O3 for DPLL, the PIs feeding the counters can be chosen to have different phase step values. Each PI has 32 possible step values that choose one of the 32 divided phases of the VCO or DCO cycle. During static phase shift, only the 0,4,8, …,28 step values can be chosen. The minimum phase resolution achieved by the PI is given by (replace VCO by DCO in the equation for DPLL):

Note that even though the phase difference between the counters in ps remains unchanged by the divide ratio of the counters, the phase difference in degrees varies depending on the divide ratio. Expressed as degrees relative to output, the minimum phase resolution is:

For example, by choosing phase step 0 for PI0 and phase step 16 for PI1, a nominal phase difference of 0.5 × VCO period or 0.5 x DCO period between the output of O0 and O1 can be achieved. For undivided clocks, this translates to a phase difference of 180 degrees. However, if both the counters are in divide-by-2 mode, the phase difference between them is 90 degrees. If both the counters are in divide-by-4 mode, the phase difference between them is 45 degrees.

In addition, each counter is capable of adding an additional phase shift that can be multiples of the VCO period or DCO period. Translating this to degrees at the output of the counters, each counter can add an additional phase shift with a resolution of 360/CLKOUT_DIVIDE degrees. The maximum phase shift range is also determined by the CLKOUT_DIVIDE value. The maximum phase shift is 360° when CLKOUT_DIVIDE is less than or equal to 256. When CLKOUT_DIVIDE is > 256, the maximum phase shift is:

The phase shift can be provided as a negative number. This is implemented by just adding 360° to the negative phase to get a positive phase value. Therefore, the negative phase shift range is –360 to maximum positive phase shift 360.

It is possible to phase shift the CLKFBOUT feedback clock. In that case all CLKOUT output clocks are negatively phase shifted with respect to CLKIN. The PI step value and the counter delay value would be automatically determined from the CLKFBOUT_PHASE and CLKOUT[0:6]_PHASE values.