Versal Adaptive SoC Clocking Resources Architecture Manual (AM003)

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1.5 English

BUFGMUX_CTRL is a clock buffer with two clock inputs, one clock output, and a select line. This primitive is based on BUFGCTRL with some pins connected to logic High or Low. The following figure illustrates the relationship of BUFGMUX_CTRL and BUFGCTRL.


BUFGMUX_CTRL uses the S pins as select pins. S can switch anytime without causing a glitch. The setup/hold time on S is for determining whether the output passes an extra pulse of the previously selected clock before switching to the new clock. If S changes as shown in the following figure prior to the setup time TBCCCK_S and before I0 transitions from High to Low, the output does not pass an extra pulse of I0. If S changes following the hold time for S, the output passes an extra pulse. If S violates the setup/hold requirements, the output might pass the extra pulse but it will not glitch. In any case, the output changes to the new clock within three clock cycles of the slower clock.

The setup/hold requirements for S0 and S1 are with respect to the falling clock edge, not the rising edge as for CE0 and CE1. Switching conditions for BUFGMUX_CTRL are the same as the S pin of BUFGCTRL. The following figure illustrates the timing diagram for BUFGMUX_CTRL.

Figure 2. BUFGMUX_CTRL Timing Diagram

Other capabilities of the BUFGMUX_CTRL primitive areas follows.

  • I0 and I1 inputs can be preselected after configuration
  • Initial output can be selected as High or Low after configuration