Versal Adaptive SoC Clocking Resources Architecture Manual (AM003)

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1.5 English

DPLL is an MMCM lite version of the phase locked loop (PLL) that is situated in the clocking column next to the HDIO and GT clocking column. Additional DPLLs are co-located in the same tile with MMCMs. DPLLs serve as a digital version of the MMCM for frequency synthesizers for a wide range of frequencies, and as jitter filters for either external or internal clocks, and deskew clocks. In many respects the functionality and capability of a DPLL are similar to that of MMCM and XPLL. Many of the DPLL functions can be found in the MMCMs section. Some of the differences are frequency specifications.

The fundamental, functional operation of the DPLL can be described as follows:

The time to digital converter (TDC) and accumulators measure the phase offset and frequency ratio of the input (reference) clock and the oscillator clock. They create a code that is fed to a digital loop filter (DLF). The output of the DLF determines the frequency of the digital controlled oscillator (DCO). It being a digital implementation loop filter, adjustments only occur every positive clock edge. The DCO produces eight output phases which feed the 4 phase interpolators (PIs). Each PI output generates the input clock for each of the 4 output counters. Each counter can be independently programmed for a given design. A frequency control word (FCW) providing the reference phase, is the division ratio command responsible for generating the multiply value for frequency synthesis. Therefore, unlike in the MMCM, there is no distinct feedback counter/divider.

Unlike the MMCM, the DPLL does not have a SDM module for fractional divide.

Figure 1. DPLL Block Diagram