Multi-Clock Buffers - Multi-Clock Buffers - AM003

For high-speed synchronous clock domain crossings in previous architectures, it was common to use several clocks, generated by the same MMCM, with power of 2 ratios. In such cases, users generated clocks with separate MMCM outputs, used BUFGCE cells to drive the clock loads or created the divided clocks with parallel BUFGCE_DIV cells driven by the fastest MMCM output. Those clock buffers were placed close to the clock managers and often caused timing challenges due to the amount of uncertainty introduced in the paths between source and destination clocks. In designs with synchronous paths between clocks, the routing delay matching implementation option (CLOCK_DELAY_GROUP) is needed to minimize the clock-domain-crossing skew, and limit the impact on setup and hold fixing. In larger devices, timing closure between clock domains can turn out to be very challenging and users, therefore, often make the choice to add logic, FIFOs, and treat clock paths as asynchronous paths.

With the Versal device, a multi-clock buffer (MBUFG) can be used to generate up to four clocks close to the leaf clock pins instead of at the output of the XPLL, MMCM, or DPLL. This reduces the clock pessimism impact on synchronous clock-domain-crossing paths and helps solve design timing more efficiently. Basically, there is a single route to the BUFDIV_LEAF cell that does the division at the leaf driver level. Each MBUFG type buffer uses the corresponding BUFG site, for example MBUFGCE is placed on the BUFGCE site and so on.

When on a MBUFG-type clock buffer and the MODE attribute is set to PERFORMANCE, the outputs of that clock buffer behave as follows:

• Output O1 = Input I
• Output O2 = Input I divided by 2
• Output O3 = Input I divided by 4
• Output O4 = Input I divided by 8

There are five types of MBUFG or multi-clock buffers: MBUFGCTRL, MBUFGCE, MBUFGCE_DIV, MBUFG_PS, and MBUFG_GT, as shown in the following figure. The multi-clock buffers have the same input pins as the respective equivalent BUFGCTRL, BUFGCE, BUFGCE_DIV, BUFG_PS, and BUFG_GT clock buffers (also described in this manual), but it has four different outputs.

The multi-clock buffers are logical-only clock buffers that use the equivalent BUFGs plus the physical-only BUFDIV_LEAF clock buffers to divide the clock closer to the loads. This removes the insertion delay from the clock buffer to the leaf clocks and reduces clock skew on synchronous clock domain crossing (CDC) paths. Many designs use multiple simple clock buffers divide-by-n clock buffers, where n can be 2, 4, or 8, and the MBUFG handles multiple instantiated buffers by offering a single buffer. The CLRB_LEAF input on the MBUFG primitives is used to asynchronously reset the BUFDIV_LEAF dividers. For more information on CLRB_LEAF reset requirements for MBUFG, refer to the Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387).

MBUFGCTRL

This primitive is designed as a synchronous/asynchronous glitch-free multiplexer with two clock inputs and multiple outputs. If clock multiplexing is not necessary, use the MBUFGCE component.

MBUFGCE

This primitive is designed as a clock buffer with enable/disable possibilities with single clock input and multiple outputs.

MBUFG_GT

This primitive is designed as a clock buffer by the gigabit transceiver devices for the purpose of clock distribution with minimal clock pessimism to other parts of the design. In addition to the MODE attribute setting, the behavior of the outputs also changes based on the value of pins DIV[2:0]. The divide value is (setting value + 1), for example, setting 3'b000 means a divide value of 1 and 3'b111 means a divide value of 8.

MBUFG_PS

This primitive is designed as a multi-output high fanout buffer for low skew distribution of the PS clock signals.

MBUFGCE_DIV

This primitive is designed as a multi-output clock buffer with an enable, clear, and divide function. In addition to the MODE attribute setting, MBUFGCE_DIV uses the same BUFGCE_DIVIDE attribute as BUFGCE_DIV. Setting the attribute to a value other than 1 results in further division of the output clock by that factor.