Clock Buffers

Versal Adaptive SoC Clocking Resources Architecture Manual (AM003)

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Global clocks are a dedicated network of interconnects specifically designed to reach all clock inputs to the various resources in a device. These networks are designed to have low skew and low duty cycle distortion, low power, and improved jitter tolerance. They are also designed to support very high-frequency signals.

The maximum achievable frequency of a global clock network in Versal devices is dependent on the clock routing and clock extent. To maximize the frequency that a global clock network can support, follow the recommendations listed here. For details on how to implement the recommendations, see the Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387).

  • Minimize the clock routing distance to the clock root
  • Set the clock root to the central clock region in the clock expansion window
  • Avoid clock routing in the GT column by assigning the clock root in the PL clock region

In the Vivado tools 2023.1 and later, the Vivado timer automatically computes the Fmax for each clock net based on the clock routing and reports slack under worst pulse width slack (WPWS) in the timing summary report.

Understanding the signal path for a global clock expands the understanding of the various global clocking resources. The global clocking resources and network consist of these paths and components:

  • Clock structure
  • Clock buffers
  • BUFGCTRL clock buffer primitives
  • Additional BUFGCTRL use models
  • BUFGCE and BUFGCE_DIV clock buffers
  • BUFG clock buffer
  • BUFG_GT clock buffer
  • BUFG_PS clock buffer
  • BUFG_FABRIC buffer (for routing high fanout non-clock nets, not a global clock resource)

All buffers are described later in this chapter.