XPLL Primitive

Versal Adaptive SoC Clocking Resources Architecture Manual (AM003)

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1.5 English

The Versal device XPLL primitive is shown in the following figure.

Figure 1. XPLL Primitive

The XPLL is a mixed-signal block designed to support clock network deskew, frequency synthesis, and jitter reduction. These three modes of operation are discussed in more detail in this section. The VCO operating frequency can be determined using the following relationship:

where the M, D, and O counters are shown in Figure 1. The value of M corresponds to the CLKFBOUT_MULT_F setting, the value of D to the DIVCLK_DIVIDE, and O to the CLKOUT_DIVIDE.

The five O counters can be independently programmed. For example, O0 can be programmed to do a divide-by-two while O1 is programmed for a divide-by-three. The only constraint is that the VCO operating frequency must be the same for all the output counters because a single VCO drives all the counters.