Table 1 shows the minimum current, in addition to ICCQ maximum, required by each Zynq UltraScale+ RFSoC for proper power-on and configuration. If these current minimums are met, the device powers on after all supplies have passed through their power-on reset threshold voltages. The device must not be configured until after VCCINT is applied. Once initialized and configured, use the Xilinx Power Estimator (XPE) to estimate current drain on these supplies. The XPE tool (download at https://www.xilinx.com/power) is also used to estimate power-on current for all supplies.
ICC Min = | ICCINTMIN | ICCINT_IOMIN + ICCBRAMMIN | ICCOMIN | ICCAUXMIN + ICCAUX_IOMIN | ICCSDFECMIN | Units |
---|---|---|---|---|---|---|
ICCQ + | ICCINTQ + | ICCBRAMQ + ICCINT_IOQ + | ICCOQ + | ICCAUXQ + ICCAUX_IOQ + | ICCSDFECQ + | |
XCZU21DR XQZU21DR |
4500 | 770 | 50 | 320 | 250 | mA |
XCZU25DR | 4500 | 770 | 50 | 320 | 250 | mA |
XCZU27DR | 4500 | 770 | 50 | 320 | 250 | mA |
XCZU28DR XQZU28DR |
4500 | 770 | 50 | 320 | 250 | mA |
XCZU29DR XQZU29DR |
4500 | 1020 | 50 | 320 | N/A | mA |
XCZU39DR | 4500 | 1020 | 50 | 320 | N/A | mA |
XCZU42DR | 3516 | 602 | 50 | 261 | N/A | mA |
XCZU43DR | 4500 | 1020 | 50 | 320 | N/A | mA |
XCZU46DR | 4500 | 1020 | 50 | 320 | 250 | mA |
XCZU47DR | 4500 | 1020 | 50 | 320 | N/A | mA |
XCZU48DR XQZU48DR |
4500 | 1020 | 50 | 320 | 250 | mA |
XCZU49DR XQZU49DR |
4500 | 1020 | 50 | 320 | N/A | mA |
XCZU63DR | 3516 | 602 | 50 | 261 | N/A | mA |
XCZU64DR | 3516 | 602 | 50 | 261 | N/A | mA |
XCZU65DR XQZU65DR |
3516 | 602 | 50 | 261 | N/A | mA |
XCZU67DR XQZU67DR |
3516 | 602 | 50 | 261 | N/A | mA |
Symbol | Description | Min | Max | Units |
---|---|---|---|---|
TVCCINT | Ramp time from GND to 95% of VCCINT | 0.2 | 40 | ms |
TVCCINT_IO | Ramp time from GND to 95% of VCCINT_IO | 0.2 | 40 | ms |
TVCCO | Ramp time from GND to 95% of VCCO | 0.2 | 40 | ms |
TVCCAUX | Ramp time from GND to 95% of VCCAUX | 0.2 | 40 | ms |
TVCCBRAM | Ramp time from GND to 95% of VCCBRAM | 0.2 | 40 | ms |
TMGTAVCC | Ramp time from GND to 95% of VMGTAVCC | 0.2 | 40 | ms |
TMGTAVTT | Ramp time from GND to 95% of VMGTAVTT | 0.2 | 40 | ms |
TMGTVCCAUX | Ramp time from GND to 95% of VMGTVCCAUX | 0.2 | 40 | ms |
TVCC_PSINTFP | Ramp time from GND to 95% of VCC_PSINTFP | 0.2 | 40 | ms |
TVCC_PSINTLP | Ramp time from GND to 95% of VCC_PSINTLP | 0.2 | 40 | ms |
TVCC_PSAUX | Ramp time from GND to 95% of VCC_PSAUX | 0.2 | 40 | ms |
TVCC_PSINTFP_DDR | Ramp time from GND to 95% of VCC_PSINTFP_DDR | 0.2 | 40 | ms |
TVCC_PSADC | Ramp time from GND to 95% of VCC_PSADC | 0.2 | 40 | ms |
TVCC_PSPLL | Ramp time from GND to 95% of VCC_PSPLL | 0.2 | 40 | ms |
TPS_MGTRAVCC | Ramp time from GND to 95% of VCC_MGTRAVCC | 0.2 | 40 | ms |
TPS_MGTRAVTT | Ramp time from GND to 95% of VCC_MGTRAVTT | 0.2 | 40 | ms |
TVCCO_PSDDR | Ramp time from GND to 95% of VCCO_PSDDR | 0.2 | 40 | ms |
TVCC_PSDDR_PLL | Ramp time from GND to 95% of VCC_PSDDR_PLL | 0.2 | 40 | ms |
TVCCO_PSIO | Ramp time from GND to 95% of VCCO_PSIO | 0.2 | 40 | ms |
TVADC_AVCC | Ramp time from GND to 95% of VADC_AVCC | 0.2 | 40 | ms |
TVADC_AVCCAUX | Ramp time from GND to 95% of VADC_AVCCAUX | 0.2 | 40 | ms |
TVDAC_AVCC | Ramp time from GND to 95% of VDAC_AVCC | 0.2 | 40 | ms |
TVDAC_AVCCAUX | Ramp time from GND to 95% of VDAC_AVCCAUX | 0.2 | 40 | ms |
TVDAC_AVTT | Ramp time from GND to 95% of VDAC_AVTT | 0.2 | 40 | ms |
TVCCSDFEC | Ramp time from GND to 95% of VCCSDFEC | 0.2 | 40 | ms |