Device Pin-to-Pin Output Parameter Guidelines - DS926

Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926)
Document ID
DS926
Release Date
2024-12-23
Revision
1.14 English

The pin-to-pin numbers in the following tables are based on the clock root placement in the center of the device. The actual pin-to-pin values will vary if the root placement selected is different. Consult the Vivado Design Suite timing report for the actual pin-to-pin values.

Table 1. Global Clock Input to Output Delay Without MMCM (Near Clock Region)
Symbol Description 1 Device Speed Grade and VCCINT Operating Voltages Units
0.85V 0.72V
-2 -1 -2 -1
SSTL15 Global Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without MMCM
TICKOF Global clock input and output flip-flop without MMCM (near clock region) XCZU21DR 6.26 6.73 7.80 8.36 ns
XCZU25DR 6.05 6.50 7.55 8.09 ns
XCZU27DR 6.26 6.73 7.80 8.36 ns
XCZU28DR 6.26 6.73 7.80 8.36 ns
XCZU29DR 6.26 6.73 7.80 8.36 ns
XCZU39DR 6.26 N/A 7.80 N/A ns
XCZU42DR 6.28 6.77 7.86 8.42 ns
XCZU43DR 6.26 6.73 7.80 8.36 ns
XCZU46DR 6.26 6.73 7.80 8.36 ns
XCZU47DR 6.26 6.73 7.80 8.36 ns
XCZU48DR 6.26 6.73 7.80 8.36 ns
XCZU49DR 6.26 6.73 7.80 8.36 ns
XCZU63DR 6.28 6.77 7.86 8.42 ns
XCZU64DR 6.28 6.77 7.86 8.42 ns
XCZU65DR 6.28 6.77 7.86 8.42 ns
XCZU67DR 6.28 6.77 7.86 8.42 ns
XQZU21DR 6.26 6.73 N/A 8.36 ns
XQZU28DR 6.26 6.73 N/A 8.36 ns
XQZU29DR 6.26 6.73 N/A 8.36 ns
XQZU48DR 6.26 6.73 7.80 8.36 ns
XQZU49DR 6.26 6.73 7.80 8.36 ns
XQZU65DR 6.28 6.77 7.86 8.42 ns
XQZU67DR 6.28 6.77 7.86 8.42 ns
  1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible I/O and CLB flip-flops are clocked by the global clock net.
Table 2. Global Clock Input to Output Delay Without MMCM (Far Clock Region)
Symbol Description 1 Device Speed Grade and VCCINT Operating Voltages Units
0.85V 0.72V
-2 -1 -2 -1
SSTL15 Global Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without MMCM
TICKOF_FAR Global clock input and output flip-flop without MMCM (far clock region) XCZU21DR 6.89 7.39 8.64 9.27 ns
XCZU25DR 6.48 6.96 8.11 8.71 ns
XCZU27DR 6.89 7.39 8.64 9.27 ns
XCZU28DR 6.89 7.39 8.64 9.27 ns
XCZU29DR 6.89 7.39 8.64 9.27 ns
XCZU39DR 6.89 N/A 8.64 N/A ns
XCZU42DR 6.05 6.51 7.64 8.20 ns
XCZU43DR 6.89 7.39 8.64 9.27 ns
XCZU46DR 6.89 7.39 8.64 9.27 ns
XCZU47DR 6.89 7.39 8.64 9.27 ns
XCZU48DR 6.89 7.39 8.64 9.27 ns
XCZU49DR 6.89 7.39 8.64 9.27 ns
XCZU63DR 6.05 6.51 7.64 8.20 ns
XCZU64DR 6.05 6.51 7.64 8.20 ns
XCZU65DR 6.05 6.51 7.64 8.20 ns
XCZU67DR 6.05 6.51 7.64 8.20 ns
XQZU21DR 6.89 7.39 N/A 9.27 ns
XQZU28DR 6.89 7.39 N/A 9.27 ns
XQZU29DR 6.89 7.39 N/A 9.27 ns
XQZU48DR 6.89 7.39 8.64 9.27 ns
XQZU49DR 6.89 7.39 8.64 9.27 ns
XQZU65DR 6.05 6.51 7.64 8.20 ns
XQZU67DR 6.05 6.51 7.64 8.20 ns
  1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible I/O and CLB flip-flops are clocked by the global clock net.
Table 3. Global Clock Input to Output Delay With MMCM
Symbol Description 1, 2 Device Speed Grade and VCCINT Operating Voltages Units
0.85V 0.72V
-2 -1 -2 -1
SSTL15 Global Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with MMCM
TICKOFMMCMCC Global clock input and output flip-flop with MMCM XCZU21DR 2.31 2.53 2.97 3.13 ns
XCZU25DR 2.28 2.49 2.96 3.12 ns
XCZU27DR 2.31 2.53 2.97 3.13 ns
XCZU28DR 2.31 2.53 2.97 3.13 ns
XCZU29DR 2.31 2.53 2.97 3.13 ns
XCZU39DR 2.31 N/A 2.97 N/A ns
XCZU42DR 2.22 2.43 2.87 3.02 ns
XCZU43DR 2.31 2.53 2.97 3.13 ns
XCZU46DR 2.31 2.53 2.97 3.13 ns
XCZU47DR 2.31 2.53 2.97 3.13 ns
XCZU48DR 2.31 2.53 2.97 3.13 ns
XCZU49DR 2.31 2.53 2.97 3.13 ns
XCZU63DR 2.22 2.43 2.87 3.02 ns
XCZU64DR 2.22 2.43 2.87 3.02 ns
XCZU65DR 2.22 2.43 2.87 3.02 ns
XCZU67DR 2.22 2.43 2.87 3.02 ns
XQZU21DR 2.31 2.53 N/A 3.13 ns
XQZU28DR 2.31 2.53 N/A 3.13 ns
XQZU29DR 2.31 2.53 N/A 3.13 ns
XQZU48DR 2.31 2.53 2.97 3.13 ns
XQZU49DR 2.31 2.53 2.97 3.13 ns
XQZU65DR 2.22 2.43 2.87 3.02 ns
XQZU67DR 2.22 2.43 2.87 3.02 ns
  1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible I/O and CLB flip-flops are clocked by the global clock net.
  2. MMCM output jitter is already included in the timing calculation.
Table 4. Source Synchronous Output Characteristics (Component Mode)
Description Speed Grade and VCCINT Operating Voltages Units
0.85V 0.72V
-2 -1 -2 -1
TOUTPUT_LOGIC_DELAY_VARIATION 1 80 ps
  1. Delay mismatch across a transmit bus when using component mode output logic (ODDRE1, OSERDESE3) within a bank.