Integrated Interface Block for PCI Express Designs

Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926)

Document ID
DS926
Release Date
2024-05-31
Revision
1.13 English

More information and documentation on solutions for PCI Express® designs can be found at PCI Express . The UltraScale Architecture and Product Data Sheet: Overview (DS890) lists how many PCIE4 or PCIE4C blocks are in each Zynq UltraScale+ RFSoC. The PCIE4C blocks are augmented with support for the CCIX protocol. For supported modes, link widths, and link speeds, see the UltraScale+ Devices Integrated Block for PCI Express LogiCORE IP Product Guide (PG213).

Table 1. Maximum Performance for PCIE4-based PCI Express Designs for ZU2xDR and ZU39DR Devices
Symbol Description Speed Grade and VCCINT Operating Voltages Units
0.85V 0.72V
-2 -1 -2 -1
FPIPECLK Pipe clock maximum frequency 250.00 250.00 250.00 250.00 MHz
FCORECLK Core clock maximum frequency 500.00 500.00 250.00 250.00 MHz
FDRPCLK DRP clock maximum frequency 250.00 250.00 250.00 250.00 MHz
FMCAPCLK MCAP clock maximum frequency 125.00 125.00 125.00 125.00 MHz
Table 2. Maximum Performance for PCIE4C-based PCI Express and CCIX Designs for ZU4xDR and ZU6xDR Devices
Symbol Description Speed Grade and VCCINT Operating Voltages Units
0.85V 0.72V
-2 -1 -2 -1
FPIPECLK Pipe clock maximum frequency 250.00 250.00 250.00 250.00 MHz
FCORECLK Core clock maximum frequency 500.00 500.00 500.00 250.00 MHz
FCORECLKCCIX CCIX TL interface clock maximum frequency 500.00 500.00 N/A N/A MHz
FDRPCLK DRP clock maximum frequency 250.00 250.00 250.00 250.00 MHz
FMCAPCLK MCAP clock maximum frequency 125.00 125.00 125.00 125.00 MHz