Revision History - DS926

Updated description of V_CCO for HP I/O banks in Table 1 and Table 1.

In Table 3, changed minimum F_S for PLL bypassed, dual ADC tile configuration to 1000 MHz. Updated note about internal PLL to say "clock" instead of "carrier" in Table 3 and Table 4.

Added note about V_IN for POR_OVERRIDE pin to Table 1 and Table 1.

Expanded V_CCO table note into Notes 9 and 10 in Table 1.

Updated Note 7 in Table 2 and Note 10 in Table 4.

In Table 3, updated DRAM type descriptions, and consolidated 2-rank 1-slot and LPDDR4 notes.

Added maximum values for ACLR in Table 5 and Table 10.

Added maximum values for NSD, HD3, IM3, GTIS, and OIS, and minimum values for SFDR in Table 6 and Table 11.

Added maximum values for ACLR, NSD, HD3, and IM3, and minimum values for SFDR to Table 7 and Table 8.

Updated note 2 in Configuration Switching Characteristics.

Added the production released XCZU63DR and XCZU64DR devices to Table 1, Table 1, and Table 1 in Vivado Design Suite 2023.1 v1.30, and where applicable in other sections of this data sheet.

Added note about Quad-SPI feedback clock MIO[6] pin to Table 1 and Table 2.

Updated introductory paragraph in Integrated Interface Block for PCI Express Designs.

Removed mention of I/Os being tristated at power-on from PS Power-On/Off Power Supply Sequencing.

Revised the Production Specification speed specification version in Table 1 to Vivado Design Suite from 2021.2.2 to 2022.1.

Replaced "die" with "rank" for LPDDR4 DRAM type in Table 3.

Updated to PCIe Gen1, 2, 3, 4 protocol in Table 1.

Clarified low-power devices that support only one V_CCINT voltage in Summary.

Added Note 12 to Table 1: ADC maximum inputs are only valid when both ADC supplies are present.

Added the production released XQZU65DR and XQZU67DR devices to Table 1, Table 1, and Table 1 in Vivado Design Suite 2021.2.2 v1.30, and where applicable in other sections of this data sheet.

Added -1M to sample rate conditions in Table 4.

Updated note about RF-ADC sampling rate in Table 5, Table 6, Table 10, and Table 11.

Updated sample rate conditions and note 3 in Table 3 and Table 4.

Updated HD3 and IM3 parameters in Table 6. Updated IM3 parameters in Table 11. Updated SFDR parameters in Table 8.

Updated maximum V_IN value and note 4 in Table 3 and Table 4.

Added the production released XCZU42DR, XCZU65DR, and XCZU67DR devices to Table 1, Table 1, and Table 1 in Vivado Design Suite 2021.2.1 v1.29, and where applicable in other sections of this data sheet.

Updated Note 1 and Note 17 in Table 1.

Updated introductory paragraph in Available Speed Grades and Operating Voltages. Added Note 1 to Table 1.

For clarity, moved the location of the specifications for internal V_REF, differential termination, and temperature diode (ideality factor and series resistance) in Table 1.

Added Note 7 to Table 3: LPDDR3 quad die package devices are not supported.

Added Note 1 to Table 1.

Added RX Sync and TX Sync parameters to Table 3.

Added notes for full scale range and ADC bandwidth to Table 3.

Added note about ACLR performance to Table 3 and Table 8.

Added note about HD2 measurement to Table 4, Table 9, Table 7, and Table 8.

Added DC coupling row to output current range and updated note about variable output power effective dynamic range in Table 3.

Added note about derating of 1.5 dB to Table 5 and Table 6.

Updated comments/conditions for RX sync and TX sync and updated Note 6 in Table 4.

Added DFE Integrated Blocks.

Decreased the 0 dB maximum attenuation in Table 3, Table 8, and the NSD averaged across the first nyquist zone in Table 4, and Table 9. Added E/I and M speed grade rows to HD3 and IM3 in Table 9.

Added E/I and M speed grade rows to SFDR in Table 6.

Reduced the maximum sample rate in RF-DAC Electrical Characteristics.

Added the production released XCZU43DR, XCZU46DR, XCZU47DR, XCZU48DR, and XCZU49DR devices to Table 1, Table 1, and Table 1 in Vivado Design Suite 2020.2 v1.30, and where applicable in other sections of this data sheet.

Revised the Summary to include specific voltages by device.

Updated the symbol name V_{RFDC_CLK_IN} in Absolute Maximum Ratings.

Added Note 7 to Table 2. Added Note 10 to Table 4.

Revised symbol and description of IOPLL_TO_FPD maximum frequency in Table 5.

To specify that the PS-GTR for PCI Express is only supported by the common clock architecture, added Note 1 to Table 5.

Added the capability for XC devices designing with Vivado Design Suite v2019.1.1 or later to increase the performance of the MIPI PHY transmitter/receiver in Table 3.

Added the RF-ADC/RF-DAC to PL Interface Switching Characteristics section.

Increased the maximum line rate of the QPLL0 -1 (V_CCINT = 0.85V) output divider 1 in Table 1 and updated Notes 2 and 3.

Reorganized the Integrated RF-ADC Block and Integrated RF-DAC Block sections and the notes where the typical values are now specified at 40°C. Updated the typical Return Loss conditions and notes in each section. In the RF-ADC Electrical Characteristics section, Table 3, updated the common mode voltage descriptions. Clarified the meaning of all of the OIS parameter descriptions in the RF-ADC Performance Characteristics section. Updated the sampling rate Note 1 and revised the sample F_REF to 250 MHz in Table 1, Table 2, and Table 7.

Added Table 5.

Production released the XCZU39DR device in -2I (V_CCINT = 0.85V) and -2LI (V_CCINT = 0.72V) speed/temperature grades throughout the data sheet for Vivado Design Suite 2019.1 v1.23

In the Integrated Interface Block for Interlaken section, removed package-specific limitation.

Added the production released XQZU21DR and XQZU29DR devices in the -2I, -1I, -1M, and -1LI speed/temperature grades to Table 1, Table 1, and Table 1 in Vivado Design Suite 2018.3 or 2018.3.1 v1.23.

This version also adds the ruggedized FFRD1156 and FFRF1760 packages to support the XQZU21DR and XQZU29DR.

Updated Table 1 to Vivado Design Suite 2018.3.1 v1.23.

Add the XQZU21DR and XQZU29DR devices to Table 1, Table 1, Table 1, Table 2, Table 3, Table 1, Table 2, and Table 1.

Updated Note 1 in Table 2.

Added LVDS component mode notes to Programmable Logic (PL) Performance Characteristics.

Added the production released XQZU28DR device in the -2I, -1I, -1M, and -1LI speed/temperature grades to Table 1, Table 1, and Table 1 in Vivado Design Suite 2018.3 v1.23.

Added military grade T_j to Table 1 and -1M to Table 1.

Add the XQZU28DR devices to Table 1, Table 1, Table 1, Table 2, Table 3, Table 1, Table 2, and Table 1.

Added the FFRE1156 and FFRG1517 packages to Table 1 and the Integrated Interface Block for Interlaken section.

Updated Note 22 in Table 1.

Updated Note 3 in Table 1, Table 2, Table 3. Updated the V_IDIFF description in Table 1. Revised minimum PS DDR data rates for all I-grade devices in Table 3.

Updated the speed grade notes in Table 6.

In Table 1, removed Note 1.

Removed PCI Express Gen4 support in Table 1 and Note 1, Note 2, and Note 3.

In Table 1, added M-grade NSD F_IN = 3.5 GHz, the HD3 F_IN = 2.4 GHz, and IM3 F_IN = 3.5 GHz, F1, F2 at –7 dBFS and 20 MHz delta.

In Table 1, added M-grade ACLR F_C = 3.5 GHz.

In Table 3, added M-grade ACLR F_C = 240 MHz, and NSD F_OUT = 3.5 GHz CW at –10 dBFS.

Added the MTS sync specification to Table 1.

Added Note 22 to Table 1.

Where applicable, added the -2LI (V_CCINT = 0.72V) speed/temperature grade specifications throughout this data sheet. Updated Table 1, Table 1, and Table 1 to production for the following devices/speed/temperature grades in Vivado Design Suite 2018.2.1 v1.21.

XCZU21DR: -1LI (V_CCINT = 0.85V), and -2LI, -1LI (V_CCINT = 0.72V)

XCZU25DR: -1LI (V_CCINT = 0.85V), and -2LI, -1LI (V_CCINT = 0.72V)

XCZU27DR: -1LI (V_CCINT = 0.85V), and -2LI, -1LI (V_CCINT = 0.72V)

XCZU28DR: -1LI (V_CCINT = 0.85V), and -2LI, -1LI (V_CCINT = 0.72V)

XCZU29DR: -1LI (V_CCINT = 0.85V), and -2LI, -1LI (V_CCINT = 0.72V)

In Table 2, added RF-DAC, RF-ADC, and SD-FEC power supply values.

Added the -2LI specific values to Table 2 and added Note 4 to the LVDS RX DDR maximum data.

Added -2LI specific values to Table 5, Table 1, Table 1, and Table 1.

In Table 6 added Note 4.

In Table 2, added -2LI.

In Table 1, revised the calculated values from 322.223 to 322.266. Added Note 1.

Edited Note 2 in Table 1.

In Table 1, clarified the parameter description of F_IN , revised the maximum ratio of R and added Note 2, updated the minimum PLL output frequency range to 500 MHz, and revised Note 6.

In Table 1, added Notes 1 and 2.

Added the RF-DAC/RF-ADC power supply sequencing information to the PL Power-On/Off Power Supply Sequencing section.

Updated Table 1, Table 1, and Table 1 to production for the following devices/speed/temperature grades in Vivado Design Suite 2018.2 v1.20.

XCZU21DR: -2E, -2I, -2LE, -1E, -1I (V_CCINT = 0.85V), and -2LE (V_CCINT = 0.72V)

XCZU25DR: -2E, -2I, -2LE, -1E, -1I (V_CCINT = 0.85V), and -2LE (V_CCINT = 0.72V)

XCZU27DR: -2E, -2I, -2LE, -1E, -1I (V_CCINT = 0.85V), and -2LE (V_CCINT = 0.72V)

XCZU28DR: -2E, -2I, -2LE, -1E, -1I (V_CCINT = 0.85V), and -2LE (V_CCINT = 0.72V)

XCZU29DR: -2E, -2I, -2LE, -1E, -1I (V_CCINT = 0.85V), and -2LE (V_CCINT = 0.72V)

Added Table 1.

Updated the specifications in Table 1, Table 2, Table 3, Table 1, and Table 2. Added package skew data to Table 1.

Revised the speed grade -1 (V_CCINT = 0.85) F_GTYMAX in Table 1, which also revised values in Table 6 and added Note 7.

Revised and added data to Table 1, Table 1, Table 7, Table 1, Table 3, and Table 1. In Table 1, revised Note 7.