PS Gigabit Ethernet Controller Interface

Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926)

Document ID
DS926
Release Date
2024-05-31
Revision
1.13 English
Table 1. RGMII Interface
Symbol Description 1 Min Max Units
TDCGEMTXCLK Transmit clock duty cycle 45 55 %
TGEMTXCKO TXD output clock to out time –0.5 0.5 ns
TGEMRXDCK RXD input setup time 0.8 ns
TGEMRXCKD RXD input hold time 0.8 ns
TMDIOCLK MDC output clock period 400 ns
TMDIOCKL MDC low time 160 ns
TMDIOCKH MDC high time 160 ns
TMDIODCK MDIO input data setup time 80 ns
TMDIOCKD MDIO input data hold time 0.0 ns
TMDIOCKO MDIO output data delay time –1.0 15 ns
FGETXCLK RGMII_TX_CLK transmit clock frequency 125 MHz
FGERXCLK RGMII_RX_CLK receive clock frequency 125 MHz
FENET_REF_CLK Ethernet reference clock frequency 125 MHz
  1. The test conditions are configured to the LVCMOS 2.5V I/O standard with a 12 mA drive strength, fast slew rate, and a 15 pF load.