More information and documentation on solutions using the integrated interface block for Interlaken can be found at UltraScale+ Interlaken . The UltraScale Architecture and Product Data Sheet: Overview (DS890) lists how many blocks are in each Zynq UltraScale+ RFSoC. This section describes the following Interlaken configurations.
Symbol | Description | Speed Grade and VCCINT Operating Voltages | Units | |||||||
---|---|---|---|---|---|---|---|---|---|---|
0.85V | 0.72V | |||||||||
-2 | -1 | -2 | -1 | |||||||
FRX_SERDES_CLK | Receive serializer/ deserializer clock | 195.32 | 195.32 | 195.32 | 195.32 | MHz | ||||
FTX_SERDES_CLK | Transmit serializer/ deserializer clock | 195.32 | 195.32 | 195.32 | 195.32 | MHz | ||||
FDRP_CLK | Dynamic reconfiguration port clock | 250.00 | 250.00 | 250.00 | 250.00 | MHz | ||||
Min 1 | Max | Min 1 | Max | Min 1 | Max | Min 1 | Max | |||
FCORE_CLK | Interlaken core clock | 300.00 | 322.27 | 300.00 | 322.27 | 300.00 | 322.27 | 300.00 | 322.27 | MHz |
FLBUS_CLK | Interlaken local bus clock | 300.00 | 322.27 | 300.00 | 322.27 | 300.00 | 322.27 | 300.00 | 322.27 | MHz |
|
Symbol | Description | Speed Grade and VCCINT Operating Voltages | Units | |||||||
---|---|---|---|---|---|---|---|---|---|---|
0.85V | 0.72V | |||||||||
-2E/-2I/-2LE 1 | -1E/-1I/-1M/-1LI | -2LE | -2LI/-1LI | |||||||
FRX_SERDES_CLK | Receive serializer/ deserializer clock | 440.79 | N/A | 402.84 | N/A | MHz | ||||
FTX_SERDES_CLK | Transmit serializer/ deserializer clock | 440.79 | N/A | 402.84 | N/A | MHz | ||||
FDRP_CLK | Dynamic reconfiguration port clock | 250.00 | N/A | 250.00 | N/A | MHz | ||||
Min 2 | Max | Min | Max | Min 2 | Max | Min | Max | |||
FCORE_CLK | Interlaken core clock | 412.50 3 | 479.20 | N/A | 412.50 | 429.69 | N/A | MHz | ||
FLBUS_CLK | Interlaken local bus clock | 300.00 4 | 349.52 | N/A | 300.00 | 349.52 | N/A | MHz | ||
|
Symbol | Description | Speed Grade and VCCINT Operating Voltages | Units | |||
---|---|---|---|---|---|---|
0.85V | 0.72V | |||||
-2 | -1 | -2 | -1 | |||
FRX_SERDES_CLK | Receive serializer/ deserializer clock | 402.84 | N/A | N/A | N/A | MHz |
FTX_SERDES_CLK | Transmit serializer/ deserializer clock | 402.84 | N/A | N/A | N/A | MHz |
FDRP_CLK | Dynamic reconfiguration port clock | 250.00 | N/A | N/A | N/A | MHz |
FCORE_CLK | Interlaken core clock | 412.50 | N/A | N/A | N/A | MHz |
FLBUS_CLK | Interlaken local bus clock | 349.52 | N/A | N/A | N/A | MHz |